Title:
SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/185153
Kind Code:
A1
Abstract:
Provided is a semiconductor device having a novel configuration. This semiconductor device comprises a cell array which performs multiply-add operations in a first layer and multiply-add operations in a second layer in an artificial neural network, a first circuit which inputs data into the cell array, and a second circuit which outputs second data from the cell array. The cell array comprises multiple cells. The cell array has a first region and a second region. During a first period, in the first region, by inputting the t^th (t a natural number greater than or equal to 2) first data from the first circuit, the t^th second data corresponding to multiply-add operations in the first layer is outputted to the second circuit. In the second region, by inputting the (t-1)^st first data from the first circuit, the (t-1)^st second data corresponding to the multiply-add operations in the second layer is outputted to the first circuit.
Inventors:
KUROKAWA YOSHIYUKI (JP)
GODO HIROMICHI (JP)
TSUDA KAZUKI (JP)
OHSHITA SATORU (JP)
RIKIMARU HIDEFUMI (JP)
GODO HIROMICHI (JP)
TSUDA KAZUKI (JP)
OHSHITA SATORU (JP)
RIKIMARU HIDEFUMI (JP)
Application Number:
PCT/IB2022/051619
Publication Date:
September 09, 2022
Filing Date:
February 24, 2022
Export Citation:
Assignee:
SEMICONDUCTOR ENERGY LAB (JP)
International Classes:
G06G7/60; G06N3/063; G09F9/30; G09G3/20; G09G3/3233; H01L21/336; H01L21/822; H01L21/8234; H01L21/8242; H01L27/04; H01L27/06; H01L27/088; H01L27/108; H01L27/1156; H01L29/786; H01L29/788; H01L29/792; H01L51/50; H05B33/02
Foreign References:
| JP6489295B1 | 2019-03-27 | |||
| JP2016219011A | 2016-12-22 |
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