RELATED APPLICATIONS

[0001] The present application claims the benefit under 35 U.S.C. 119(e) of U.S. Provisional Application 61/715,330 filed on 18 October 2012, the disclosure of which is incorporated herein by reference in its entirety.

FIELD

[0002] Embodiments of the invention relate to a method of fabricating semiconductor devices.

BACKGROUND

[0003] A semiconductor device ("SD") is typically fabricated, through a photolithographic process, in arrays containing large numbers of the devices on a semiconductor wafer, such as a Si, SiC, GaAs, or GaN wafer. In a photolithographic process, a photoresist layer applied onto the wafer is patterned with light exposure using a stepper. The stepper exposes selected portions of the wafer to a pattern of light (a "reticle light pattern") that is created by projecting light through a reticle, typically a transparent material with opaque patterns (for example, chrome patterns on a quartz sheet). The reticle light pattern is miniaturized and projected onto the photoresist layer through the use of appropriate optics, typically at multiple locations on the surface of the wafer. The exposed photoresist layer is then developed, creating a pattern of openings defined by the reticle light patterns. The pattern of the photoresist openings defines where on the surface of the wafer a fabrication step, for example deposition or etching, takes place.

[0004] After SD fabrication is completed, the wafer is separated, "diced", into pieces referred to as "dies", each of which comprises a single copy of the device.

[0005] SDs are susceptible to be rendered defective as a result of an accumulation of fabrication defects, which can reduce the number of functional SDs that can be produced from one wafer ("die yield"). After SD fabrication on the wafer is complete but before the wafer is diced, the completed SD are subjected to wafer screening to assess the die yield, in which each SD is tested for functional defects. Typically, the screening test is performed with an electronic tester, commonly referred to as a wafer prober, which includes a probe card comprising a set of microscopic probes. The probes are placed on a set of conductive pads situated on the surface of each completed SD, which are connected to the SD's internal circuitry. The probes apply test patterns to the SD and record readout from the SD through the conductive pads. Through the screening process, the SDs are sorted into "good SDs" that meet predetermined test criteria and "bad SDs" that fail to meet the criteria. Additionally, the wafer testing may include optical testing of the SDs. The sorting data, including the status of each SD and its location on the wafer, may be logged on an electronic "substrate map" (a "wafer map" if the substrate map covers the entire wafer), which can be used to guide subsequent assembly and packaging.

[0006] Die yields, especially in non-mature processes like SD fabrication on GaN or SiC wafers, or in the fabrication of large SDs that cover a wide wafer surface area, may be very low. Die yield improvement is a goal in SD fabrication, as it directly impacts the number of functional dies that can be fabricated relative to materials and manufacturing costs.

SUMMARY

[0007] An aspect of an embodiment of the invention relates to providing a SD fabrication method, also referred to as a "redundancy-based fabrication method", in which the SDs are tested during the fabrication process, before the SDs are completed. The SDs (also referred to as "redundant cluster SDs" or "RCSDs") comprise a plurality of clusters of active component cells ("clusters"), out of which only a predetermined number (a "target count"), which is less than the total number of clusters, are required be functional for the RCSD to be good. RCSDs are tested in a partially fabricated state, after the clusters are fabricated but before the clusters are interconnected within the RCSD, in order to identify functional and defective clusters. In each good RCSD having at least the target count of functional clusters, the target count of functional clusters are selected as "active clusters" and the remaining clusters (functional or defective) are selected as "orphan clusters". In subsequent fabrication of the RCSD, the active clusters are interconnected within the RCSD and the orphan clusters are left unconnected.

[0008] In accordance with an embodiment of the invention, the redundancy-based fabrication method may comprise: producing on a wafer at least one RCSD having a number of clusters greater than the desired plurality of clusters; testing the produced clusters for acceptable functioning; and interconnecting a number of acceptably functioning clusters equal to the desired plurality.

[0009] For convenience of presentation, the process of performing the screening test and selecting the active and orphan clusters based on the screening test results may be referred to herein as an "intermediate testing phase", and the process of interconnecting the active clusters within the RCSD may be referred to herein as a "cluster interconnection phase". [0010] For convenience of presentation, the partially fabricated RCSD with clusters that are configured to be accessible to screening tests may be referred to as "test phase RCSDs", and a wafer having the test phase RCSDs may be referred to as a "test phase wafer".

[0011] As used herein, with respect to wafers and its constituent SDs and clusters, "horizontal" refers to the orientation that is substantially parallel to the surface of the wafer and "vertical" refers to the orientation that is substantially perpendicular to the surface of the wafer. As used herein with regard to the wafer and components therein, "lateral", "next to", "adjacent" and the like refer to spatial relationships in the horizontal orientation. As used herein with regard to the wafer and components therein, "the top", "on top of, "above" and the like refer to spatial relationships in the vertical orientation at or towards the side of the wafer that SD fabrication takes place, and "the bottom", "under", "underneath" and the like refer to spatial relationships in the vertical orientation at or towards the opposite side of the wafer.

[0012] In accordance with an embodiment of the invention, each cluster may include an "active area" where the active component cells are situated, and may optionally include a "perimeter" free of active component cells that laterally surrounds (fully or partially) the active area. The active component cells may be, for example, diodes and field effect transistors (FETs). The clusters may comprise an array of substantially identical active components cells. Alternatively, each cluster may be a modular circuit having a combination of different active component cells. In accordance with an embodiment of the invention, the RCSD may comprise multiple types of clusters that are interconnected with each other. Alternatively, each cluster in the RCSD may be substantially identical.

[0013] In accordance with an embodiment of the invention, each cluster of the test phase RCSD may have a plurality of "probe pads" that are conductive pads connected to the internal circuitry of the cluster, through which electrical properties of the cluster may be measured for performing functional screening tests. In accordance with an embodiment of the invention, the probe pads are configured to make contact or be aligned with probes on a probe card connected to a wafer prober.

[0014] According to an embodiment of the invention, each cluster of the test phase RCSD includes a plurality of conductive pads ("interconnect pads") on its top surface that serve as contacts through which the active clusters are interconnected within the RCSD. Like the probe pads, the interconnect pads are connected to the internal circuitry of the cluster. In certain embodiments of the invention, the interconnect pads may be a separate set of contact pads in addition to the probe pads. Alternatively, the interconnect pads and the probe pads on each cluster may be the same set of conductive pads, which serve as probe pads during the intermediate testing phase and as interconnect pads during the cluster interconnection phase.

[0015] According to an embodiment of the invention, the interconnecting of the active clusters may comprise conductively connecting pairs of adjacent active clusters. Such an "adjacent cluster interconnection scheme" may include interconnecting active clusters within the RCSD through a photolithographic process that forms an interconnect layer comprising conductive patches that conductively connect pairs of interconnect pads between adjacent active clusters.

[0016] According to an embodiment of the invention, the photolithographic process reproduces a set of conductive patches on each active cluster in a predetermined pattern. A photoresist layer is applied on the test-phase wafer following the intermediate test phase. Using a stepper, a photoresist layer is exposed to a reticle light pattern at the location of each active cluster. The reticle light pattern comprises a set of defined regions (also referred to as a set of "patch templates") where light is directed by the stepper onto the photoresist layer. The patch templates, as exposed on the photoresist layer at the active cluster locations, are converted into a pattern of conductive patches by the photolithographic process.

[0017] In accordance with an embodiment of the invention, the pairs of interconnect pads on adjacent clusters that are connected by a conductive patch (provided that the adjacent clusters are active) may be predetermined based on the location of each interconnect pad on the cluster surface and the configuration of the set of patch templates in relation to the cluster.

[0018] For convenience of presentation, the predetermined pair of interconnect pads may be referred to herein as "partner pads".

[0019] In accordance with an embodiment of the invention, a patch template includes at least a portion of one interconnect pad and a portion of the adjacent cluster without including the partner pad on the adjacent cluster. Consequently, when both adjacent clusters are active clusters, the two patch templates that include each of the partner pad pair overlap, so that one contiguous conductive patch that conductively connects the pair of partner pads is formed through the photolithographic process.

[0020] In the discussion, unless otherwise stated, adjectives such as "substantially", "relatively" and "about" modifying a condition or relationship characteristic of a feature or features of an embodiment of the invention, are understood to mean that the condition or characteristic is defined to within tolerances that are acceptable for operation of the embodiment for an application for which it is intended. Unless otherwise indicated, the word "or" in the specification and claims is considered to be the inclusive "or" rather than the exclusive or, and indicates at least one of, or any combination of items it conjoins.

[0021] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.

BRIEF DESCRIPTION OF FIGURES

[0022] Non-limiting examples of embodiments of the invention are described below with reference to figures attached hereto that are listed following this paragraph. Identical structures, elements or parts that appear in more than one figure are generally labeled with a same numeral in all the figures in which they appear. Dimensions of components and features shown in the figures are chosen for convenience and clarity of presentation and are not necessarily shown to scale.

[0023] Fig. 1 schematically illustrates, in perspective view, a wafer having a plurality of test phase RCSDs, with an inset showing, in overhead view, a single RCSD die having a plurality of clusters, in accordance with an embodiment of the invention;

[0024] Fig. 2 shows a flowchart of a redundancy-based fabrication method;

[0025] Fig. 3A schematically illustrates, in an overhead view, a group of four adjacent RCSD dies, each RCSD die with functional clusters (plain) and defective clusters (marked with X), as determined by a screening test;

[0026] Fig. 3B schematically illustrates, in an overhead view, the group of RCSD dies shown in Fig. 2A, with a target count of functional clusters (dark) selected as active clusters, with the remaining clusters (good or bad) selected as orphan clusters (white);

[0027] Fig. 4A schematically illustrates, in a perspective view, an exemplary cluster having a set of first probe pads, a set of second probe pads, a set of first interconnect pads and a set of second interconnect pads;

[0028] Fig. 4B schematically illustrates, in an overhead view, an exemplary reticle light pattern that is shone on an active cluster of Fig. 4A;

[0029] Fig. 4C schematically illustrates, in overhead view, a 1 x 3 array of the cluster of Fig.

4A, with two of the three clusters schematically indicated to have been exposed to the reticle light pattern of Fig. 4B;

[0030] Fig. 4D schematically illustrates, in a perspective view, an exemplary RCSD having a 4 x 4 array of the cluster of Fig. 4A after the application of conductive patches; [0031] Fig. 5 schematically illustrates an alternative cluster having a set of third probe pads (along with sets of first and second probe pads) and a set of third interconnect pads (along with sets of first and second interconnect pads), as well as an alternative reticle light pattern;

[0032] Fig. 6A schematically illustrates, in an overhead view, an alternative cluster having a first conductive pad and a second conductive pad, with an exemplary reticle light pattern;

[0033] Fig. 6B schematically illustrates, in overhead view, a 2 x 3 array of the cluster of Fig.

6A, with five of the six clusters schematically indicated to have been exposed to the reticle light pattern of Fig. 6A;

[0034] Fig. 6C schematically illustrates, in perspective view, the 2 x 3 cluster array of Fig.

6C after the formation of conductive patches based on the reticle light pattern shone on the active clusters as shown in Fig. 6B;

[0035] Fig. 6D schematically illustrates, in perspective view, an exemplary RCSD having a 4 x 6 array of the cluster of Fig. 6A after the application of conductive patches;

[0036] Fig. 7A schematically illustrates, in overhead view, the cluster of Fig. 6A with an alternative set of patch templates;

[0037] Fig. 7B schematically illustrates, in perspective view, an exemplary 2 x 3 array of the cluster of Fig. 7A after the formation of conductive patches based on the reticle light pattern exposed to five active clusters out of the six total clusters; and

[0038] Fig. 8 schematically illustrates, in an overhead view, an alternative cluster having a first conductive pad, a second conductive pad and a third conductive pad, the conductive pads serving as probe pads in the intermediate testing phase and as interconnect pads in the cluster interconnect phase, as well as a set of patch templates for the alternative cluster.

DETAILED DESCRIPTION

[0039] In the following detailed description, a wafer having exemplary RCSDs in accordance with an embodiment of the invention are schematically illustrated in Fig. 1 and discussed with reference to that figure. A redundancy-based fabrication method in accordance with an embodiment of the invention is shown as a flowchart in Fig. 2 and schematically illustrated in Figures 3A-3B, and discussed with reference to those figures. Exemplary clusters, steps of the cluster interconnect phase and interconnected RCSDs in accordance with an embodiment of the invention are schematically illustrated in Figs. 4A-4D, 5, 6A-6D, 7A-7B, and 8, and discussed with reference to those figures. [0040] Reference is now made to Fig. 1 showing a schematic view of a wafer 10 having a plurality of rectangular RCSDs 20 in an array, in accordance with an embodiment of the invention.

[0041] In accordance with an embodiment of the invention, wafer 10 may optionally be a Si wafer, a SiC wafer, a GaAs wafer, a GaN wafer, a GaN on Si wafer or a GaN on SiC wafer.

[0042] According to an embodiment of the invention, RCSD 20 may be a power SD, optionally a power diode or a power FET. In certain embodiments of the invention, the power SD may be a lateral power SD, optionally a lateral power diode or a lateral power FET. In certain embodiments of the invention, RCSD 20 may be one of other SDs as known in the art, for example, a RAM chip, a flash memory chip, a field emitter array, or a system on a chip (SOC).

[0043] As shown in the inset to Fig. 1 , each RCSD 20 includes multiple clusters 30, and each cluster 30 comprises multiple active component cells (not shown). In certain embodiments of the invention, each cluster may comprise a plurality of substantially identical active components. Alternatively, each cluster may be a modular circuit having a combination of different types of active component cells. In certain embodiments of the invention, at least a portion of a current is carried within the active component cell by a two dimensional electron gas ("2DEG").

[0044] According to an embodiment of the invention, the number of clusters 30 in each SD 20 is in excess of a target count of cluster 30 required for the operation of SD 20 (that is, for SD 20 to be good). As such, each RCSD is characterized by a redundancy of clusters 30. In accordance with an embodiment of the invention, the plurality of clusters 30 in RCSD 20 may comprise multiple cluster types that are interconnected with each other. RCSD 20 may have a redundancy of each cluster type. Alternatively, each cluster 30 in RCSD 20 may be substantially identical.

[0045] In certain embodiments of the invention, each RCSD 20 may optionally cover a wafer

2 2 2 surface area of about 15 square millimeters (mm ), about 20 mm , about 25 mm , about 30 mm 2 , about 50 mm 2 , about 75 mm 2 , about 100 mm 2 , or about 150 mm 2. Optionally, the number of RCSD on a wafer may be at most 50, at most 75, at most 100, at most 150, at most 200, at most 250, at most 300, at most 350, at most 400, at most 450, or at most 500. Optionally, the number of clusters 30 in each RCSD may be least 10, at least 25, at least 50, at least 75, at least 100, at least 150, at least 200, between 10 and 200, between 50 and 100, or between 75 and 150. Optionally, the number of active component cells (not shown in Fig. 1) in each cluster may be about 20, about 30, about 40, about 50, about 75 or about 100. It will be appreciated that the number of active component cells in each cluster, the surface area of each cluster, the number of clusters in each RCSD and the surface area of each RCSD are interrelated.

[0046] As described above, RCSD 20 may be a lateral power diode or a lateral power FET.

Power SDs, including lateral power SDs, are advantageously characterized by being capable of safely passing relatively high "ON currents" when they are ON, and having relatively high breakdown voltages when they are OFF.

[0047] The ON and OFF states of a power FET is controlled by changing the gate source voltage. In the ON state, the power FET is capable of passing the ON current between source and drain, which may be characterized, for example by the source drain voltage and the RDS(on) (drain source resistance at ON state). In the OFF state, the power FET only allows a leakage current that is smaller than the ON current between the source and drain. The breakdown voltage in a power FET is the source drain voltage at which the power FET can be made to pass more current than the leakage current in the OFF state. Applying a source drain voltage at or beyond the breakdown voltage when the power FET is OFF may be damaging to the power FET.

[0048] Power diodes are ON when they are forward biased and OFF when they are reverse biased (or not sufficiently forward biased). In the ON state, the power diode is capable of passing an ON current between anode and cathode. In the OFF state, the power diode only allows a leakage current that is smaller than the ON current between the anode and cathode. The breakdown voltage in a power diode is the reverse bias voltage at which the power diode can be made to pass more current than the leakage current. Applying a reverse bias voltage at or beyond the breakdown voltage may be damaging to the power diode.

[0049] According to an embodiment of the invention, RCSD 20 may be a lateral power diode or a lateral power FET that is capable of passing a relatively high ON current and have a relatively high breakdown voltage. In certain embodiments of the invention, the relatively high ON current may be a continuous current of at least 20 A, at least 25 A, at least 30 A, at least 35 A, at least 40 A or at least 50 A. In certain embodiments of the invention, the relatively high breakdown voltage may be at least 300 Volts (V), at least 400 V, at least 500 V, at least 600 V or at least 700 V.

[0050] With reference to Fig. 2, there is provided a redundancy-based fabrication method 200 for fabricating RCSDs (for example RCSD 20 of Fig. 1) according to an embodiment of the invention, the method comprising: performing a screening test on a test phase wafer having a plurality of test phase RCSDs to identify functional clusters and defective clusters within each RCSD (210); selecting, in each good test phase RCSD having at least a target count of functional clusters, functional clusters equal to the target count to be active clusters (220); selecting the remaining clusters in the good RCSD to be orphan clusters (230); and interconnecting the active clusters within the good RCSDs (240).

[0051] According to an embodiment of the invention, the screening test may optionally include functional tests or include functional tests and optical tests. The screening test may include a plurality of individual tests, with each cluster that passes all (or a predetermined portion) of the individual tests being identified as functional clusters and the remaining clusters that fail one or more individual tests being identified as defective clusters.

[0052] The functional test of the clusters may be performed with a probe card connected to a wafer prober. The wafer prober used in performing the screening tests for the clusters of the embodiments of the invention may be a standard wafer prober used in the wafer screening of fully fabricated SDs. The designing and manufacturing of probe cards having an appropriate number of probes in an appropriate spatial arrangement, as needed, is known in the art.

[0053] According to an embodiment of the invention, each cluster of the test phase RCSD includes multiple probe pads. The probe pads and the probe card are configured to be compatible, such that when the probe card is placed on the cluster surface, each probe makes contact or is aligned with the appropriate probe pad. In certain embodiments of the invention, the wafer prober may be a contact-based system, where the probes of the probe card and the probe pads on the clusters make physical contact to form a conductive connection. Alternatively, the wafer prober may be a wireless, non-contact wafer testing system, where the probes and the probe pads function as radio frequency (RF) antennae, so that proximity, but not physical contact, is required for functional testing to take place. The screening tests performed by the wafer prober on the clusters may depend on the circuitry of the cluster. By way of example, the RCSD may be a power FET, with each cluster having a plurality of FET cells connected in parallel. The functional test for such clusters may include the measurement of RDS(on) (drain source resistance at ON state), gate leakage current, drain source leakage current, breakdown voltage and the like.

[0054] In accordance with an embodiment of the invention, the probe pads may optionally be situated on top of the active area and/or on top of the perimeter. The number of probe pads on each cluster may depend on the circuitry of the cluster. By way of example, each of the clusters in a power diode RCSD may have at least one "anode probe pad" to which the anodes from the diode cells in the cluster are connected and at least one "cathode probe pad" to which the cathodes from the diode cells in the cluster are connected. Where the RCSD is a power FET, the clusters may have at least one "source probe pad" to which the sources from the FET cells in the cluster are connected, at least one "drain probe pad" to which the drains from the FET cells in the cluster are connected and at least one "gate probe pad" to which the gates from the FET cells in the cluster are connected. Various configurations of probe pads will be discussed in further detail hereinbelow.

[0055] Fig. 3A schematically illustrates four adjacent RCSDs on a wafer, showing the result of a screening test on RCSDs 20A-20D. Each RCSD 20 has an 8 x 8 array of sixty four (64) clusters 30, with the functional clusters unmarked and the defective clusters being marked schematically with a X-shaped mark. RCSD 20A has 7 defective clusters and 57 functional clusters. RCSD 20B has 10 defective clusters and 54 functional clusters. RCSD 20C has 4 defective clusters and 60 functional clusters. RCSD 20D has 12 defective clusters and 52 functional clusters.

[0056] Fig. 3B schematically illustrates the same RCSD of Fig. 3A, following the selection of active clusters (shaded) and orphan clusters (white). Each of RCSDs 20A-20D has a target count of 54 functional clusters out of the total of 64 clusters. In accordance with an embodiment of the invention, RCSDs having less functional clusters than the target count are sorted as a bad RCSD and RCSDs having at least the target count are sorted as good RCSDs. As such, RCSD 20D having 52 functional clusters is sorted as a bad RCSD (and thus indicated as such schematically with a large X-shaped mark) and RCSDs 20A-20C having 54 or more functional clusters are sorted as good RCSDs.

[0057] In accordance with an embodiment of the invention, in the good RCSDs, functional clusters equal in number to the target count are selected to be active clusters, the remaining functional clusters (if any) are selected to be orphan clusters, and all of the defective clusters are selected to be orphan clusters. As shown in Fig. 3B, each of RCSD 20A-20C has fifty four active clusters (shaded) even though each of RCSD 20A-20C has a different number of defective clusters. In RCSD 20A with 10 defective clusters and 54 functional clusters, all defective clusters are selected as orphan clusters and all functional clusters are selected as active clusters. In RCSDs 20B, 54 out of the 57 functional clusters are selected to be active clusters, and the remaining 3 functional clusters, together with 7 defective clusters, are selected to be orphan clusters. In RCSD 20C, 54 out of the 60 function RCSDs are selected to be active cluster, and the remaining 6 functional clusters, together the 4 defective clusters, are selected to be orphan clusters.

[0058] As described with reference to Fig. 3B, in accordance with an embodiment of the invention, the functional clusters may be selected to be either active clusters or orphan clusters according to the following scheme: If the number of functional clusters is equal to the target count, then all functional clusters are selected to be active clusters and all defective clusters are selected to be orphan clusters; and if there are more functional clusters than the target count, then a subset of the functional clusters equal in number to the target count are selected to be active clusters and the remaining functional clusters as well as the defective clusters are selected to be orphan clusters.

[0059] While having RCSDs with excess clusters may increase the proportion of good dies fabricated out of the total dies on the wafer, it also increases the size of each die, thus reducing the total number of dies (good or bad) fabricated on each wafer. Thus, for the redundancy-based manufacturing method to increase die yield, that is, the number of good dies produced per wafer, the increase in the proportion of good dies out of the total dies on the wafer must be sufficiently high to offset the reduction in the total number of dies per wafer.

[0060] By way of numerical example, we fabricated (or attempted to fabricate) a power FET capable of passing an ON current of about 30 Amperes (A) and having a breakdown voltage of about 600V using two methods. The first method was a standard fabrication method in which the power FET had no redundant clusters. The second method was a redundancy-based fabrication method as provided in an embodiment of the invention, in which the power FETs were RCSDs with excess clusters, and the test phase RCSDs were functionally tested to identify functional and defective clusters.

[0061] In the standard method, 314 power FET dies, were produced on a GaN wafer having a 4-inch diameter. Each die was 6 mm x 3 mm in size with 64 clusters. For the power FET to have the predetermined desired functional criteria, such as being capable of passing an ON current of about 30 A, having a breakdown voltage of about 600 V and having a predefined RDS(on) . All 64 clusters were required to be functional for the power FET to be good (in other words, the power FET had no redundant clusters). The power FET was fabricated without an intermediate testing step and all 64 clusters were interconnected within the power FET, regardless of whether or not the clusters were functional. Out of the 314 resulting power FET dies, only a few dies, for example, less than 10 dies, were good dies that met the desired functional criteria.

[0062] In the redundancy-based manufacturing method, the power FET was configured as a RCSD having 81 clusters (the clusters being substantially identical to the clusters fabricated in the first method) with a target count of 64 functional clusters. That is, the RCSD die required 64 functional clusters (out of the 81 total) to meet the predetermined desired functional criteria of being able to pass an ON current of about 30 A, having a breakdown voltage of about 600 V, and having a predefined RDS _(on) . Each RCSD die was 6 mm x 4 mm, and 248 dies were fabricated on a 4-inch-diameter GaN wafer substantially identical to the wafer used in the first method. As a part of the redundancy-based manufacturing method, the clusters in each RCSD were subjected to a screening test during an intermediate testing phase to identify functional and defective clusters. The RCSDs having less than 64 functional clusters were sorted as bad RCSDs. In the good RCSDs having at least 64 functional clusters, 64 functional clusters were selected to be active clusters and interconnected within the power FET. The remaining 17 clusters were selected as orphan clusters and left unconnected. Out of the 248 power FET dies fabricated on the wafer with the redundancy-based manufacturing method, 200 dies were good dies that met the desired functional criteria and 48 dies were bad dies.

[0063] In accordance with an embodiment of the invention, and as described with reference to the flowchart of Fig. 2, the active clusters, once selected, are interconnected within the RCSD in the cluster interconnect phase. In accordance with an embodiment of the invention, the status of each cluster in the test phase wafer (for example as functional, defective, active and/or orphan), as determined in the intermediate testing phase, may be logged on a substrate map, and the substrate map may be used in guiding the cluster interconnection phase.

[0064] In certain embodiments of the invention, the active clusters may be interconnected through an adjacent cluster interconnection scheme that creates, through a lithographic process, a single interconnect layer comprising a pattern of conductive patches that conductively connect partner pads. The conductive patches may comprise one or more of elemental metals such as aluminum, gold copper, nickel or titanium, or a metal alloy.

[0065] Fig. 4A schematically illustrates, in a perspective view, a single cluster 130 having an active area 138 laterally surrounded by a perimeter 139. Typically, a plurality of clusters 130 are arranged in an array in an RCSD (not shown in Fig. 4A). Each cluster 130 includes two first probe pads 132 (white) and a two second probe pads 134 (shaded) situated on top of an active area 138. Each of two first probe pads 132 are substantially identical, and are conductively connected with each other through the internal circuitry of cluster 130. Similarly, each of two second probe pads 134 are substantially identical, and are conductively connected with each other through the internal circuitry of cluster 130.

[0066] Cluster 130 further includes four first interconnect pads 142 (white) and four second interconnect pads 144 (shaded), with one first interconnect pad and one second interconnect pad being situated on each of the four sides of cluster 130 on perimeter 139. Each of four first interconnect pads 142 are substantially identical, and are conductively connected with each other through the internal circuitry of cluster 130. Similarly, each of four second interconnect pads 144 are substantially identical, and are conductively connected with each other through the internal circuitry of cluster 130.

[0067] For convenience of presentation, a set of substantially identical probe pads on one cluster that are conductively connected with each other through the internal circuitry of the cluster may collectively be referred to as a "probe channel". Similarly, a set of substantially identical interconnect pads on one cluster that are conductively connected with each other through the internal circuitry of the cluster may collectively be referred to as an "interconnect channel". As such, cluster 130 includes a "first probe channel" having two first probe pads 132, a "second probe channel" having two second probe pads 134, "first interconnect channel" having four first interconnect pads 142 and a "second interconnect channel" having four second interconnect pads 144.

[0068] By way of example, cluster 130 may be a diode cluster comprising a plurality of diode cells connected in parallel. As such, first probe pad 132 may be an anode probe pad and second probe pad 134 may be a cathode probe pad. Similarly, first interconnect pad 142 may be an anode interconnect pad and second interconnect pad 144 may be a cathode interconnect pad.

[0069] Fig. 4B schematically illustrates an exemplary reticle light pattern comprising a set of patch templates reproduced onto each cluster 130 that is selected as an active cluster. Each patch template is schematically indicated as regions enclosed by a set of dashed rectangles 152.

[0070] For convenience of presentation, the cluster to which the plurality of patch templates is applied may be referred to as the "target cluster".

[0071] In accordance with an embodiment of the invention, a photolithographic process, as known in the art, may be used to convert the set of patch templates to a corresponding metallization pattern comprising conductive patches. The photoresist used in the photolithographic process may optionally be a positive resist or a negative resist, selected as appropriate. With a positive resist, the portions of the photoresist that is exposed to light become soluble to the photoresist developer, and the portion of the photoresist that is unexposed remains on the wafer. With a negative resist, the portion of the photoresist that is exposed to light becomes insoluble.

[0072] In certain embodiments of the invention, the photolithographic process may optionally be a Damascene approach. Alternatively, the photolithographic process may optionally be created through a lift-off process. Alternatively, the photolithographic process may optionally be based on metal etch back.

[0073] By way of example, the photolithographic process in the cluster interconnect phase described in Figs. 4A-D (as well as in the figures following Figs. 4A-4D) may be a lift-off process, a Damascene process or a metal etch back process.

[0074] In an exemplary Damascene process, following the selection of active and orphan clusters, a dielectric layer is deposited on the wafer, followed by a positive photoresist layer. Through stepper processing and photoresist developing, the patch template is reproduced as a negative pattern of photoresist openings at each active cluster, with the photoresist openings defining the areas of conductive patch application. The dielectric layer uncovered at the photoresist openings is etched, forming trenches in the dielectric layer. Metal is then applied (for example through electroplating, deposition or sputtering), on the wafer surface, filling the trenches, and the excess metal is removed by chemical-mechanical planarization ("CMP"). The metal-filled trenches serve as the conductive patches.

[0075] In an exemplary lift-off process, following the selection of active and orphan clusters, positive photoresist is deposited on the wafer. Through stepper processing and photoresist developing, the patch template is reproduced as a negative pattern of photoresist openings at each active cluster, with the photoresist openings defining the areas of conductive patch application. A thin metal layer is applied on the wafer surface (for example through electroplating, deposition or sputtering), which covers the portions of the RCSD uncovered by the photoresist openings as well as the remaining photoresist. The remaining photoresist is removed together with the metal that was deposited thereon, so that only the metal layer that was formed at the photoresist openings remain on the RCSD surface. This remaining metal layer serves as the conductive patches.

[0076] In an exemplary metal etch back process, following the selection of active and orphan clusters, a thin metal layer is applied on the wafer (for example through electroplating, deposition or sputtering) followed by a negative photoresist layer. Through stepper processing and photoresist developing, the patch template is reproduced as a positive pattern of photoresist openings at each active cluster, in which the desired location of the conductive patches remain covered by photoresist. The metal layer uncovered at the photoresist openings is etched away, and the remaining metal layer serves as the conductive patches. [0077] For clarity of presentation, the photoresist layer (and the additional dielectric layer in the case of the Damascene process) are not shown in Figs. 4A-4D (as well as in the Figures following Figs. 4A-4D).

[0078] Fig. 4C schematically illustrates a 1 x 3 array of clusters 130A-130C. Cluster 130A and 130B are active clusters and are schematically indicated to have been exposed to the reticle light pattern defined by the set of patch templates 152. Cluster 130C is an orphan cluster, and is schematically indicated as such with a X-shaped marking. Orphan cluster 130C is not exposed to the reticle light pattern.

[0079] According to an embodiment of the invention, the interconnect pads are arranged so that, at each junction between adjacent clusters, each interconnect pad is relatively close to its partner pad on the adjacent cluster. The interconnect pads are situated so that partner pads do not make physical (and thus conductive) contact, and require the application of a conductive patch in order to be conductively connected to each other. In the clusters 130 as arranged in Fig. 4C, second interconnect pads 144B and 144D on adjacent clusters are designated to be partner pads and first interconnect pads 142B and 142D are designated to be partner pads. Further, second interconnect pads 144A and 144C on adjacent clusters are partner pads and first interconnect pads 142A and 144C on adjacent clusters are partner pads. By way of example, first interconnect pad 142D of cluster 130C and first interconnect pad 142B of cluster 130B are partner pads. Similarly, second interconnect pad 144D of cluster 130C and second interconnect 144B of cluster 130B are partner pads.

[0080] In certain embodiments of the invention, the partner pads belong to the same interconnect channel, as shown by way of example in Fig. 4C. In certain embodiments of the invention, the partner pads may belong to different interconnect channels. In certain embodiments of the invention, each cluster 130 in an RCSD may have a substantially identical internal circuitry. Alternatively, an RCSD may comprise clusters 130 of different types, which have the same physical arrangement of interconnect pads and probe pads, but have different internal circuitry, optionally with the interconnect pads in one cluster 130 serving different functions from the interconnect pads of another cluster 130 within the same RCSD.

[0081] According to an embodiment of the invention, the physical arrangement of partner pads on the respective clusters as well as the shape and placement of patch templates 152 on the target cluster are configured so that one patch template 152 includes at least a portion of one interconnect pad on the target cluster and a portion of the adjacent cluster. However, patch template 152 does not include the partner pad on the adjacent cluster. At the same time, when both adjacent clusters are active clusters, the two patch templates that include each of the partner pad pair overlap, resulting in one contiguous photoresist opening as well as the subsequent formation of one contiguous conductive patch that conductively connects the pair of partner pads. By way of example, first interconnect pad 142B of active cluster 130B is included within patch template 152 while its partner pad, first interconnect pad 142D of orphan cluster 130C, is not. The resulting conductive patch (not shown) that is formed on first interconnect pad 142B of active cluster 130B fails to conductively connect its partner pad on orphan cluster 130C. By contrast, first interconnect pad 142D of active cluster 130B and its partner pad, first interconnect pad 142B of active cluster 130A are included within two patch templates 152 that overlap, and the resulting contiguous conductive patch (not shown) conductively connects the two partner pads.

[0082] Fig. 4D schematically illustrates an exemplary RCSD 120 having a 4 x 4 array of clusters 130, after the formation of conductive patches 162. The location of conductive patches 162 is based on the active clusters being exposed to the light pattern defined by the set of patch templates 152 (shown in Figs. 4B and 4C). The RCSD includes one orphan cluster, schematically indicated with an X-shaped mark. Each cluster 130 is arranged in the same orientation. RCSD 120 further includes a first lead 172 and a second lead 174.

[0083] By way of example, the RCSD may be a power diode, with first interconnect pads 142 being anode interconnect pads, second interconnect pads 144 being cathode interconnect pads, first lead 172 being an anode lead and second leas 174 being a cathode lead. The active clusters located at the periphery of the cluster array, and which laterally face anode lead 172, may be connected to anode lead 172 through the formation of conductive patches 162 on the anode interconnect pads 142 that face the anode lead. Similarly, the active clusters located at the periphery of the cluster array, and which laterally face cathode lead 174, may be connected to cathode lead 174 through the formation of conductive patches 162 on the anode interconnect pads 142 that face anode lead 172. The leads 172, 174 are sufficiently proximal to the partner pads on the peripheral clusters so that the patch template that includes each partner pad (or a portion thereof) also includes a portion of the anode lead without the need of another overlapping patch template, resulting in relatively small conductive patches that nevertheless conductively connect the partner pads to anode lead 172 and/or cathode lead 174.

[0084] As described above, each interconnect pad belonging to the same channel within one cluster are conductively connected to each other through the cluster's internal circuitry. As such, while only some of the peripheral clusters are adjacently connected to anode lead 172, the remaining active clusters that are not adjacent to anode lead 172 are also connected to anode lead 172 through the internal circuitries of the intervening clusters. Similarly, all of the active clusters, including the clusters that are not adjacent to cathode lead 174, are connected to cathode lead 174.

[0085] The single orphan cluster is not conductively connected to any of the active clusters, anode lead 172 or cathode lead 174. The conductive patches that are formed on the partner pads located on the active clusters surrounding the orphan cluster are based on a single non- overlapping patch template 152 (not shown). Therefore, the conductive patches surrounding the orphan clusters are smaller compared to the conductive patches that are formed between pairs of active clusters. The smaller conductive patches fail to reach the interconnect pads on the orphan cluster.

[0086] Fig. 5 schematically illustrates, in an overhead view, a single cluster 180 that is substantially similar in its outer structures to cluster 130, with one first probe pad 181, one second probe pad 182, a third probe channel comprising two third probe pads 183, and a third interconnect channel comprising third interconnect pads 184 situated on the perimeter. Clusters 180 may be arranged in a RCSD and interconnected in substantially the same manner as described with regard to clusters 130, with reference to Figs. 4C-4D.

[0087] By way of example, cluster 180 may be a one of a plurality of FET clusters, which are incorporated in a power FET (not shown in Fig. 5A). As such, first probe pad 181 may be a source probe pad, second probe pad 182 may be a drain probe pad and third probe pad 183 may be a gate probe pad. First interconnect pad 142 may be a source interconnect pad, second interconnect pad 144 may be a drain interconnect pad, and third interconnect pad 184 may be a gate interconnect pad.

[0088] Fig. 5 further schematically illustrates a reticle light pattern comprising a set of patch templates. The set of patch templates is schematically indicated as regions enclosed by a set of dashed rectangles 186. The set of patch templates 186 set is substantially similar to the set of patch templates 152 (shown in Fig. 4B), with the addition of four further patch templates that includes at least a portion of each gate interconnect pad 184, along with a portion of the adjacent clusters from each of the corners of cluster 180, without including its partner pads (adjacent clusters not shown in Fig. 5).

[0089] Fig. 6A schematically illustrates a single cluster 230. Cluster 230 includes a first conductive pad 242 (white) and a second conductive pad 244 (shaded). Conductive pads 242, 244 serve as probe pads in the intermediate testing phase and as interconnect pads in the cluster interconnect phase. [0090] By way of example, cluster 230 may be one of a plurality of diode clusters incorporated in a power diode. As such, first conductive pad 242 may be an anode conductive pad connected to the anodes of the diode cells in cluster 230 and second probe pad 244 may be a cathode conductive pad connected to the cathodes of the diode cells in cluster 230.

[0091] Fig. 6A further schematically illustrates a set of patch templates that define two patch templates that are schematically indicated by regions enclosed by two dashed rectangles 252. Each patch template 252 includes at least a portion of one of conductive pads 242, 244, as well as a portion of three adjacent clusters (adjacent clusters not shown in Fig. 5B).

[0092] Fig. 6B schematically illustrates a 2 x 3 array of 6 clusters 230A-230F that is a part of a larger array of 24 clusters 230 incorporated within a RCSD 220 (RCSD 200 with the full array is shown in Fig. 6C). By way of example, clusters 230 may be a diode cluster and RCSD 220 may be a power diode. According to an embodiment of the invention, diode clusters 230 are arranged in columns of alternating cluster orientations. By way of example, as shown in Fig. 6B, clusters 230A-230C are oriented so that anode conductive pads 242 are to the left of cathode conductive pads 244, while clusters 230D-230F are oriented so that anode conductive pads 242 are to the right of cathode conductive pads 244. In such an arrangement of alternating orientations, the anode conductive pad of each cluster 230 is situated to face, and be a partner pad with, anode conductive pads on up to three adjacent clusters. Similarly, the cathode conductive pad is similarly situated to be a partner pad with cathode conductive pads of up to three adjacent clusters. By way of example, cathode conductive pad 244 on cluster 230E faces, and is a partner pad with, cathode conductive pad 244 on clusters 230B, 230D and 230F.

[0093] In certain embodiments of the invention, the partner pads belong to the same interconnect channel, as shown by way of example in Fig. 6B. In certain embodiments of the invention, the partner pads may belong to different interconnect channels. In certain embodiments of the invention, each cluster 230 in an RCSD may have a substantially identical internal circuitry. Alternatively, an RCSD may comprise clusters 230 of different types, which have the same physical arrangement of interconnect pads and probe pads, but have different internal circuitry, optionally with the conductive pads in one cluster 230 serving different functions from the conductive pads of another cluster 230 within the same RCSD.

[0094] As shown in Fig. 6B, 5 out of 6 clusters 230 are active clusters that are schematically indicated to have been exposed to patterned light defined by the set of patch templates 252. Cluster 230B, which was selected as an orphan cluster and schematically indicated with an X-shaped mark, was not exposed to the reticle light pattern. Although portions along the edge of orphan cluster 230B are exposed to patterned light defined by the patch templates 252, none of the conductive pads of cluster 230B are so exposed.

[0095] According to an embodiment of the invention, the orientation-alternating arrangement of clusters 230, as well as the shape and placement of the set of patch templates 252, are configured so that one patch template 252 includes at least a portion of one conductive pad on the target cluster as well as a portion of the three adjacent clusters proximal to the conductive pad. However, the patch template does not include any of its three partner pads. At the same time, when adjacent clusters 230 are active clusters, patch templates 252 that include the partner pads (or a portion thereof) overlap. The overlapping patch templates 252 result in a contiguous photoresist opening as well as the subsequent formation of a contiguous conductive patch that conductively connects the partner pads between the adjacent active clusters.

[0096] Fig. 6C schematically illustrates the exemplary 2 x 3 array of clusters 230A-230F shown in Fig. 6B, after the formation of conductive patches 262, based on clusters 230A and 230C-230F (but not orphan cluster 230B) being exposed to the reticle light pattern defined by the set of patch templates 252 (as shown in Fig. 6B).

[0097] Fig. 6D schematically illustrates exemplary RCSD 220, which may, by way of example, be a power diode, having the 4 x 6 array of 24 clusters 230, as well as an anode lead 272 and a cathode lead 274 that laterally surround the clusters. The two orphan clusters are schematically indicated with an X-shaped mark, and the remaining clusters are active clusters. According to an embodiment of the invention, patch template 252 (not shown) is configured so that the resulting conductive patches 262 are in the form of continuous strips that are applied over multiple active clusters. It will be appreciated that due to the alternating orientation of clusters 230, "blocks" of conductive pads of the same channel are arranged, which enables them to be conductively connected by a single large, strip-shaped conductive patch. Due to conductive patches 262 forming continuous strips, anode conductive pads 242 on active clusters 230 that are not adjacent to an anode lead 272 nevertheless form a direct conductive connection with anode lead 272 without necessitating all electrical current to travel through the internal circuitry of intervening clusters (which typically have a higher resistance than the conductive patches). Similarly, cathode conductive pads 244 on active clusters 230 that are not adjacent to a cathode lead 274 nevertheless form a direct conductive connection with cathode lead 274 without necessitating all electrical current to travel through the internal circuitry of intervening clusters. [0098] Fig. 7A schematically illustrates an alternative set of patch templates for defining conductive patch formation on clusters 230, schematically indicated as regions enclosed within six dotted rectangles 253.

[0099] Fig. 7B schematically illustrates a 2x3 array of clusters 230A-F that is substantially identical to the cluster array of Fig. 6C, with the application of alternative conductive patches 263, patterned according to exposing the active clusters 230A and 230C-230F to the set of alternative patch templates 253 (shown in Fig. 7A). Orphan cluster 230B is schematically indicated with an X-shaped mark. Compared to the cluster array in Fig. 6C, in which the conductive patches form continuous strips 262 covering many clusters, conductive patches 263 are relatively small and connects pairs of partner pads between adjacent active clusters. It will be appreciated that even in this fragmented conductive patch configuration, non-adjacent clusters may form direct conductive connections through the conductive patches together with the conductive pads of intervening active clusters, without necessitating all electrical current between non-adjacent clusters to travel through the internal circuitry of intervening clusters.

[0100] Fig. 8 schematically illustrates, in an overhead view, a single cluster 330. Cluster 330 includes a first conductive pad 342, a second conductive pad 344 and a third conductive channel comprising four third conductive pads 346 situated near each corner of cluster 330. Third conductive pads 346 are functionally equivalent and are conductively connected with each other through the internal circuitry of cluster 330. Conductive pads 342, 344, 346 serve as probe pads in the intermediate testing phase and as interconnect pads in the cluster interconnect phase.

[0101] By way of example, cluster 330 may be one of a plurality of FET clusters incorporated in a power FET (not shown), each FET cluster comprising a plurality of FET cells connected in parallel. As such, first probe pad 342 may be a source conductive pad, second probe pad 344 may be a drain conductive pad, and third conductive pads 346 may be gate conductive pads.

[0102] Fig. 8 further schematically illustrates cluster 330 with a set of patch templates that are schematically indicated by six regions 352A-F outlined by dashed lines, with patch template 352A including at least a portion of conductive pad 342, patch template 352B including at least a portion of conductive pad 344, and each of patch templates 352C-F including at least a portion of one conductive pad 346.

[0103] As with clusters 230, as shown for example in Fig. 6C, clusters 330 may be arranged in a RCSD as columns of alternating cluster orientations, so that first conductive pad 342 is situated to face, and be a partner pad with, another first conductive pad 342 on up to three adjacent clusters. Similarly, the second conductive pad 344 is situated to face, and be a partner pad with, another second conductive pad 344 on up to three adjacent clusters. Further, patch template 352A and 352B are configured so that the resulting conductive patches that form on first conductive pad 342 and second conductive pad 344, respectively, are in the form of continuous strips that can each conductively connect non-adjacent active without necessitating all electrical current to travel through the internal circuitry of intervening clusters. By contrast, the four third conductive pads 346 allow for conductive connections to be made on all four sides of cluster 330. The conductive connections between non-adjacent active clusters 330 made through third conductive pads 346 are made through the internal circuitries of the intervening clusters.

[0104] In the description and claims of the present application, each of the verbs, "comprise" "include" and "have", and conjugates thereof, are used to indicate that the object or objects of the verb are not necessarily a complete listing of components, elements or parts of the subject or subjects of the verb.

[0105] Descriptions of embodiments of the invention in the present application are provided by way of example and are not intended to limit the scope of the invention. The described embodiments comprise different features, not all of which are required in all embodiments of the invention. Some embodiments utilize only some of the features or possible combinations of the features. Variations of embodiments of the invention that are described, and embodiments of the invention comprising different combinations of features noted in the described embodiments, will occur to persons of the art. The scope of the invention is limited only by the claims.