Title:
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2015/045054
Kind Code:
A1
Abstract:
A semiconductor device comprises: first pillar-shaped silicon layers (129, 131, 132, and 134); first gate dielectric layers (162) formed around the first pillar-shaped silicon layers; gate electrodes (168a and 170a), comprising metal, which are formed around the first gate dielectric layers; gate wires (168b and 170b), comprising metal, which are connected to the gate electrodes; second gate dielectric layers (173) formed around the upper portions of the first pillar-shaped silicon layers (129, 131, 132, and 134); first contacts (179a, 179b, 181a, and 181b), comprising a first metal material, which are formed around the second gate dielectric layers; second contacts (183a, 183b, 185a, and 185b), comprising a second metal material, which connect the tops of the first contacts with the tops of the first pillar-shaped silicon layers; second diffusion layers (143a and 143b) formed at the bottom of the first pillar-shaped silicon layers; and storage elements (201a, 201b, 202a, and 202b) formed above the second contacts, with variable resistance.
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Inventors:
MASUOKA FUJIO (JP)
NAKAMURA HIROKI (JP)
NAKAMURA HIROKI (JP)
Application Number:
PCT/JP2013/076031
Publication Date:
April 02, 2015
Filing Date:
September 26, 2013
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
NAKAMURA HIROKI (JP)
MASUOKA FUJIO (JP)
NAKAMURA HIROKI (JP)
International Classes:
H01L27/105
Domestic Patent References:
| WO2013093988A1 | 2013-06-27 | |||
| WO2013038553A1 | 2013-03-21 |
Foreign References:
| JP2011199017A | 2011-10-06 | |||
| JP2005260014A | 2005-09-22 | |||
| JP2010251678A | 2010-11-04 | |||
| JPH08116060A | 1996-05-07 |
Attorney, Agent or Firm:
KIMURA MITSURU (JP)
Mitsuru Kimura (JP)
Mitsuru Kimura (JP)
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