Title:
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/211974
Kind Code:
A1
Abstract:
The present invention achieves more reliable electrical connection between electrodes respectively provided at positions that face joining surfaces of substrates joined by chip lamination technology. A method for manufacturing a semiconductor device, the method being configured to include: a first step for burying electrodes in insulation layers exposed on the joining surfaces of each of a first substrate and a second substrate; a second step for performing chemical mechanical polishing on the joining surfaces of each of the first substrate and the second substrate and forming a recessed shape in which the electrodes are recessed further than the insulation layers; a third step for laminating insulation films having uniform thickness across the entirety of the joining surfaces; a fourth step for forming, by etching, openings in at least part of each of the insulation films covering the electrodes of the first substrate and the second substrate; a fifth step for causing corresponding electrodes to face each other and joining the joining surfaces of the first substrate and the second substrate; and a sixth step for heating the joined first substrate and second substrate, and causing electrode material to expand and protrude from the openings to join the corresponding electrodes.
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Inventors:
KANDA EIICHIRO (JP)
Application Number:
PCT/JP2018/017402
Publication Date:
November 22, 2018
Filing Date:
May 01, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L21/3205; H01L21/02; H01L21/60; H01L21/768; H01L23/522; H01L25/065; H01L25/07; H01L25/18; H01L27/146
Foreign References:
| JP2012019147A | 2012-01-26 | |||
| US20150108644A1 | 2015-04-23 | |||
| JP2011049270A | 2011-03-10 | |||
| JP2012019148A | 2012-01-26 | |||
| US20140353828A1 | 2014-12-04 |
Attorney, Agent or Firm:
MATSUO Kenichiro (JP)
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