Title:
SEMICONDUCTOR DEVICE AND METHOD OF PRODUCING SAME
Document Type and Number:
WIPO Patent Application WO/2011/042955
Kind Code:
A1
Abstract:
A method of producing a semiconductor device provided with an n-channel MISFET (Qn) which comprises: an Hf containing insulating film (5) which is a high permittivity gate insulating film containing hafnium, a rare earth element, and oxygen as main components; and a gate electrode (GE1) which is a metal gate electrode. The Hf containing insulating film (5) is formed by forming, from the bottom, a first Hf containing film containing hafnium and oxygen as main components, a rare-earth-containing film containing a rare earth element as a main component, and a second Hf containing film containing hafnium and oxygen as main components, then causing these to react.
Inventors:
YAMASHITA TOMOHIRO (JP)
NISHIDA YUKIO (JP)
HAYASHI TAKASHI (JP)
YAMAMOTO YOSHIKI (JP)
INOUE MASAO (JP)
NISHIDA YUKIO (JP)
HAYASHI TAKASHI (JP)
YAMAMOTO YOSHIKI (JP)
INOUE MASAO (JP)
Application Number:
PCT/JP2009/067421
Publication Date:
April 14, 2011
Filing Date:
October 06, 2009
Export Citation:
Assignee:
RENESAS ELECTRONICS CORP (JP)
YAMASHITA TOMOHIRO (JP)
NISHIDA YUKIO (JP)
HAYASHI TAKASHI (JP)
YAMAMOTO YOSHIKI (JP)
INOUE MASAO (JP)
YAMASHITA TOMOHIRO (JP)
NISHIDA YUKIO (JP)
HAYASHI TAKASHI (JP)
YAMAMOTO YOSHIKI (JP)
INOUE MASAO (JP)
International Classes:
H01L21/336; H01L21/314; H01L21/316; H01L21/8238; H01L27/092; H01L29/78
Foreign References:
| JP2009218584A | 2009-09-24 | |||
| JP2009054609A | 2009-03-12 | |||
| JP2004304053A | 2004-10-28 | |||
| JP2007529112A | 2007-10-18 | |||
| JP2002033320A | 2002-01-31 |
Other References:
K.OKAMOTO ET AL.: "Effective Control of Flat- band Voltage in Hf02 Gate Dielectric with La203 InCorporation", PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE(ESSDERC), 11 September 2007 (2007-09-11), pages 199 - 202, XP031202693, DOI: doi:10.1109/ESSDERC.2007.4430913
C.S.PARK ET AL.: "A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications", SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, 16 June 2009 (2009-06-16), pages 208 - 209
C.D.YOUNG ET AL.: "Reliability assessment of low lvtl metal high-K gate stacks for high performance applications", VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, 27 April 2009 (2009-04-27), pages 65 - 66, XP031486305
H.N.ALSHAREEF ET AL.: "Work function engineering using lanthanum oxide interfacial layers", APPLIED PHYSICS LETTERS, vol. 89, 2006, pages 232103-1 - 232103-3
C.S.PARK ET AL.: "A scalable and highly manufacturable single metal gate/high-k CMOS integration for sub-32nm technology for LSTP applications", SYMPOSIUM ON VLSI TECHNOLOGY DIGEST OF TECHNICAL PAPERS, 16 June 2009 (2009-06-16), pages 208 - 209
C.D.YOUNG ET AL.: "Reliability assessment of low lvtl metal high-K gate stacks for high performance applications", VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS, 27 April 2009 (2009-04-27), pages 65 - 66, XP031486305
H.N.ALSHAREEF ET AL.: "Work function engineering using lanthanum oxide interfacial layers", APPLIED PHYSICS LETTERS, vol. 89, 2006, pages 232103-1 - 232103-3
Attorney, Agent or Firm:
TSUTSUI, YAMATO (JP)
Tsutsui Daiwa (JP)
Tsutsui Daiwa (JP)
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