Title:
SEMICONDUCTOR DEVICE, AND POTENTIAL MEASUREMENT DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/101076
Kind Code:
A1
Abstract:
The present invention relates to: a semiconductor device which enables deterioration in signal characteristics caused by generated parasitic capacitance to be inhibited by providing a configuration which is capable of achieving an electrode plating process, when providing electrodes and an amplifier to the same substrate; and a potential measurement device. When a power supply supplies a potential required for executing plating processing, an interruption unit reads a signal from a liquid, and the signal is amplified by an amplifier and outputted, the power supply required for the plating processing is interrupted with respect to electrodes. The present invention is applicable to potential measurement devices.
Inventors:
SATO MASAHIRO (JP)
KAMETANI MACHIKO (JP)
OGI JUN (JP)
KATO YURI (JP)
KAMETANI MACHIKO (JP)
OGI JUN (JP)
KATO YURI (JP)
Application Number:
PCT/JP2017/041417
Publication Date:
June 07, 2018
Filing Date:
November 17, 2017
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
G01N27/416; C25D7/12; C25D21/12; G01R29/12
Foreign References:
| JP2012508051A | 2012-04-05 | |||
| JP2004004064A | 2004-01-08 | |||
| JP2013108831A | 2013-06-06 | |||
| JPH0678889A | 1994-03-22 | |||
| JP2002031617A | 2002-01-31 |
Other References:
See also references of EP 3550296A4
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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