Title:
SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING THE SAME
Document Type and Number:
WIPO Patent Application WO/1999/062116
Kind Code:
A1
Abstract:
A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
Inventors:
TORII KAZUYOSHI (JP)
SHIMAMOTO YASUHIRO (JP)
MIKI HIROSHI (JP)
KUSHIDA KEIKO (JP)
FUJISAKI YOSHIHISA (JP)
SHIMAMOTO YASUHIRO (JP)
MIKI HIROSHI (JP)
KUSHIDA KEIKO (JP)
FUJISAKI YOSHIHISA (JP)
Application Number:
PCT/JP1998/002274
Publication Date:
December 02, 1999
Filing Date:
May 25, 1998
Export Citation:
Assignee:
HITACHI LTD (JP)
TORII KAZUYOSHI (JP)
SHIMAMOTO YASUHIRO (JP)
MIKI HIROSHI (JP)
KUSHIDA KEIKO (JP)
FUJISAKI YOSHIHISA (JP)
TORII KAZUYOSHI (JP)
SHIMAMOTO YASUHIRO (JP)
MIKI HIROSHI (JP)
KUSHIDA KEIKO (JP)
FUJISAKI YOSHIHISA (JP)
International Classes:
H01L21/768; H01L21/8242; H01L27/108; H01L21/02; (IPC1-7): H01L21/8239; H01L21/8242; H01L27/10; H01L27/108
Foreign References:
| JPH1050956A | 1998-02-20 | |||
| JPH1093041A | 1998-04-10 | |||
| JPH08139043A | 1996-05-31 | |||
| JPH09148537A | 1997-06-06 | |||
| JPH09289296A | 1997-11-04 | |||
| JPH0846152A | 1996-02-16 | |||
| JPH0613570A | 1994-01-21 | |||
| JPH06302764A | 1994-10-28 |
Attorney, Agent or Firm:
Ogawa, Katsuo (5-1, Marunouchi 1-chom, Chiyoda-ku Tokyo, JP)
Download PDF: