Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/132568
Kind Code:
A1
Abstract:
An object is to provide technology capable of decreasing the chip area of a semiconductor element and improving the withstand-voltage performance and cut-off performance on turn-off, without degrading the performance of the element. The semiconductor device comprises: a semiconductor substrate (1) on which an active region (11) and terminal region (51) are defined; a semiconductor element (14) formed in the active region; and first to fourth P layers (38-1 to 38-4) formed in the surface of the semiconductor substrate between the edge of the active region and the terminal region. The surface concentrations (P(1) to P(4)) of the first to fourth P layers (38-1 to 38-4) decrease in this order; the bottom-edge distances (D(1) to D(4)) increase in this order; and the distances (B(1) to B(4)) as far as the edges of the semiconductor substrate increase in this order. The surface concentration (P(4)) is 10 to 1000 times the impurity concentration of the semiconductor substrate and the bottom-edge distance (D(4)) is 15 to 30 µm.
Inventors:
CHEN ZE (JP)
NAKAMURA KATSUMI (JP)
NAKAMURA KATSUMI (JP)
Application Number:
PCT/JP2012/055506
Publication Date:
September 12, 2013
Filing Date:
March 05, 2012
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
CHEN ZE (JP)
NAKAMURA KATSUMI (JP)
CHEN ZE (JP)
NAKAMURA KATSUMI (JP)
International Classes:
H01L29/06; H01L29/739; H01L29/78
Foreign References:
| JPH06334188A | 1994-12-02 | |||
| JP2001077347A | 2001-03-23 | |||
| JP2001522145A | 2001-11-13 | |||
| JP2006073740A | 2006-03-16 | |||
| JP2011204710A | 2011-10-13 |
Attorney, Agent or Firm:
YOSHITAKE Hidetoshi et al. (JP)
Hidetoshi Yoshitake (JP)
Hidetoshi Yoshitake (JP)
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