Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2015/087413
Kind Code:
A1
Abstract:
The purpose of the present invention is to employ surrounding gate transistors (SGT), a type of vertical transistor, to provide a semiconductor device of small surface area constituting a column select gate decoder. In a column select gate decoder constituted by PMOS transistors or NMOS transistors selectively connecting a plurality of bit lines and a common data line, the MOS transistors are formed on a planar silicon layer formed on a substrate, the drain, gate, and source are arranged in the vertical direction, the gate has a structure which surrounds a silicon pillar, and the planar silicon layer comprises a first activated region having a first type of conduction and a second activated region having a second type of conduction, the regions being connected to one another through a silicon layer formed on the planar silicon layer surface, thereby providing a semiconductor device of small surface area.
Inventors:
MASUOKA FUJIO (JP)
ASANO MASAMICHI (JP)
ASANO MASAMICHI (JP)
Application Number:
PCT/JP2013/083204
Publication Date:
June 18, 2015
Filing Date:
December 11, 2013
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
ASANO MASAMICHI (JP)
MASUOKA FUJIO (JP)
ASANO MASAMICHI (JP)
International Classes:
H01L27/10; H01L21/8234; H01L21/8246; H01L27/088; H01L27/112
Domestic Patent References:
| WO2009096468A1 | 2009-08-06 |
Foreign References:
| JP2000235797A | 2000-08-29 | |||
| JP2010272874A | 2010-12-02 | |||
| JPH07141869A | 1995-06-02 |
Attorney, Agent or Firm:
TSUJII Koichi et al. (JP)
辻居 Koichi (JP)
辻居 Koichi (JP)
Download PDF: