Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/139755
Kind Code:
A1
Abstract:
Provided is a highly integrated semiconductor device in which transistors are stacked. A semiconductor device provided with: a first first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first columnar semiconductor layer formed on the semiconductor layer, in which are formed in the stated order from the substrate side a second first-conductivity-type semiconductor layer, a first body region, a third first-conductivity-type semiconductor layer, a fourth first-conductivity-type semiconductor layer, a second body region, a fifth first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a third body region, and a second second-conductivity-type semiconductor layer; a first output terminal connecting the fifth first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; a second columnar semiconductor layer formed on the first output terminal, in which are formed in the stated order from the substrate side a third second-conductivity-type semiconductor layer, a fourth body region, and a fourth second-conductivity-type semiconductor layer; and gates corresponding to each body region.
Inventors:
MASUOKA FUJIO (JP)
NAKAMURA HIROKI (JP)
NAKAMURA HIROKI (JP)
Application Number:
PCT/JP2015/056247
Publication Date:
September 09, 2016
Filing Date:
March 03, 2015
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
MASUOKA FUJIO (JP)
NAKAMURA HIROKI (JP)
MASUOKA FUJIO (JP)
NAKAMURA HIROKI (JP)
International Classes:
H01L21/8234; H01L27/088
Foreign References:
| JPH0613623A | 1994-01-21 | |||
| JP2003224211A | 2003-08-08 | |||
| JP2007250652A | 2007-09-27 |
Attorney, Agent or Firm:
TSUJII Koichi et al. (JP)
辻居 Koichi (JP)
辻居 Koichi (JP)
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