Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/159057
Kind Code:
A1
Abstract:
In a gate drive circuit (2), the secondary side of a current mirror circuit (20) is formed by a PMOSFET (11) of a CMOS circuit (10). A drive capability adjustment circuit (30) receives input of an external signal adjusted by grounding any one or more of external signal input pads (34a-34c) pulled up to an internal power supply potential Vcc, and adjusts the charge capability of the PMOSFET (11) of the CMOS circuit (10) and the discharge capability of an NMOSFET (31). At the time of turn-on of an IGBT (1), a charge current to the gate of the IGBT 1 is adjusted on the basis of the potential of the ungrounded external signal input pad (34b), and at the time of turn-off, a discharge current from the gate of the IGBT (1) is adjusted by turning on an NMOSFET (31b) connected to the ungrounded external signal input pad (34b). Consequently, a semiconductor device that enables easy adjustment of drive capability and is very versatile can be provided.
Inventors:
TAKAGIWA KAZUMI (JP)
Application Number:
PCT/JP2017/002596
Publication Date:
September 21, 2017
Filing Date:
January 25, 2017
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H03K17/567; H02M1/08; H03K19/0175
Foreign References:
| JP2013031357A | 2013-02-07 | |||
| JPH09135159A | 1997-05-20 | |||
| JPH09214315A | 1997-08-15 |
Attorney, Agent or Firm:
SAKAI, Akinori (JP)
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