Title:
SEMICONDUCTOR DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/149023
Kind Code:
A1
Abstract:
The present invention can moderate stress generated in the substrate while maintaining the layout area of a semiconductor element. In a side view of a semiconductor device (1), a first end surface (3b1) of a conductive pattern (3b) is formed to be displaced inward a ceramic circuit board (3) by a first distance (d1) in the horizontal direction of a main surface of the ceramic circuit board (3) with respect to a second end surface (3c1) of a metal plate (3c). Further, a third end surface (2a1) of a semiconductor element (2) is formed to be displaced inward the ceramic circuit board (3) by a second distance (d2) in the horizontal direction of the main surface of the ceramic circuit board (3) with respect to the second end surface (3c1). Furthermore, a dimple (3c2) is formed in a predetermined range which is set apart inward the ceramic circuit board (3) from the first end surface (3b1) in the horizontal direction of the main surface of the ceramic circuit board (3).
Inventors:
ODA YOSHINORI (JP)
UEZATO YOSHINORI (JP)
UEZATO YOSHINORI (JP)
Application Number:
PCT/JP2019/046531
Publication Date:
July 23, 2020
Filing Date:
November 28, 2019
Export Citation:
Assignee:
FUJI ELECTRIC CO LTD (JP)
International Classes:
H01L23/36; H01L25/07; H01L25/18; H05K1/02
Foreign References:
| JP2015225948A | 2015-12-14 | |||
| JP2012114203A | 2012-06-14 | |||
| US20080164588A1 | 2008-07-10 | |||
| JP2006140401A | 2006-06-01 | |||
| US20180005956A1 | 2018-01-04 |
Attorney, Agent or Firm:
FUSO INTERNATIONAL PATENT FIRM (JP)
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