Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/063459
Kind Code:
A1
Abstract:
The objective of the invention is to provide, for semiconductor integrated circuit devices, a structure that can ensure an ESD protection capability for the core power supply without causing increase of the circuit area. A first pad column (20A) in a core region (2) includes a first core power supply pad (22) that is connected to a core power supply wire and externally supplied with a power supply potential or a ground potential. A pad column (20C) on the outside of the pad column (20A) includes a second core power supply pad (26) that is externally supplied with the power supply potential or ground potential common to the first core power supply pad (22) and that is connected to a core power supply I/O cell (14).
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Inventors:
MATSUI TOORU
Application Number:
PCT/JP2015/004955
Publication Date:
April 28, 2016
Filing Date:
September 29, 2015
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/822; H01L21/3205; H01L21/768; H01L21/82; H01L23/522; H01L27/04
Domestic Patent References:
| WO2011101943A1 | 2011-08-25 |
Foreign References:
| JP2008078354A | 2008-04-03 | |||
| JP2003526901A | 2003-09-09 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
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