Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/063458
Kind Code:
A1
Abstract:
The objective of the invention is to provide, for semiconductor integrated circuit devices, a structure that can sufficiently ensure an ESD protection capability and a power supply capability for I/O cells without causing increase of the circuit area. In I/O cell columns (10A, 10B), I/O cells (11A, 11B) each for supplying a power supply potential or a ground potential are connected to each other via a power supply sharing wire (31). The I/O cells (11A, 11B) are located at such positions that the I/O cells (11A, 11B) overlie each other in a first direction along which I/O cells (10) are aligned. The power supply sharing wire (31) extends in a second direction orthogonal to the first direction and is connected to first pads (21a, 21b) existing at positions that are closest to the power supply sharing wire (31) in the first direction.
Inventors:
MATSUI TOORU
YOSHIMURA MASAHIRO
YOSHIMURA MASAHIRO
Application Number:
PCT/JP2015/004938
Publication Date:
April 28, 2016
Filing Date:
September 29, 2015
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/822; H01L21/82; H01L27/04
Foreign References:
| JP2003100891A | 2003-04-04 | |||
| US20050127405A1 | 2005-06-16 | |||
| JPH03195045A | 1991-08-26 | |||
| JP2012234931A | 2012-11-29 | |||
| JP2003526901A | 2003-09-09 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
Patent business corporation MAEDA PATENT OFFICE (JP)
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