Title:
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2020/144767
Kind Code:
A1
Abstract:
Between strap power supply wirings (8a, 8b) that supply a power supply potential VDD, standard cell rows (CR1, CR3, CR5), in which, of the capacity cells (2) and the correction cells (3), only capacity cells (2) are arranged, and standard cell rows (CR2, CR4, CR6) in which, of the capacity cells (2) and the correction cells (3), only the correction cells (3) are arranged, are arranged alternately in the Y direction.
Inventors:
OCHIAI HIRONOBU (JP)
Application Number:
PCT/JP2019/000367
Publication Date:
July 16, 2020
Filing Date:
January 09, 2019
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
H01L21/82
Domestic Patent References:
| WO2017090389A1 | 2017-06-01 | |||
| WO2013132841A1 | 2013-09-12 |
Foreign References:
| JP2008277788A | 2008-11-13 | |||
| JP2001148464A | 2001-05-29 | |||
| JP2007234857A | 2007-09-13 | |||
| JP2016130919A | 2016-07-21 | |||
| JP2002110798A | 2002-04-12 | |||
| JP2005142226A | 2005-06-02 | |||
| JP2001358221A | 2001-12-26 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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