SEMICONDUCTOR INTEGRATED CIRCUIT AND MODULE MOUNTING SAME

WIPO Patent Application WO/2013/008587

A1

The purpose of the present invention is to eliminate a placement direction restriction for amplifier elements on a semiconductor chip surface. A first final-stage amplifier element (Q3) of a first RF power amplifier (100) is formed on the surface of a semiconductor chip and along a first edge thereof, and a second final-stage amplifier element (Q2) of a second RF power amplifier (500) is formed along a second edge perpendicular to the first edge. The first and second final-stage elements (Q3 and Q2) are configured from multiple unit transistors. The multiple unit transistors contain active regions (G) having rectangular planar geometry. The extension direction of the longer edges of multiple rectangles in multiple unit transistors of the first and second final-stage elements (Q3 and Q2) is set in the length direction of the second edge. The direction of iterative enlargement for multiple unit transistors in the first final-stage element (Q3) is set in the length direction of the first edge, and the direction of iterative enlargement for multiple unit transistors in the second final-stage element (Q2) is set in the length direction of the second edge.

NAGURA KENICHI (JP)
OKANO MASASHI (JP)
NAKAJIMA SHIZUKI (JP)
OBU ISAO (JP)

PCT/JP2012/065584

January 17, 2013

June 19, 2012

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MURATA MANUFACTURING CO (JP)
NAGURA KENICHI (JP)
OKANO MASASHI (JP)
NAKAJIMA SHIZUKI (JP)
OBU ISAO (JP)

H01L21/331; H01L21/822; H01L21/336; H01L21/8234; H01L27/04; H01L27/088; H01L29/732; H01L29/737; H01L29/78; H03F3/24; H03F3/68

JP2007173314A	2007-07-05
JP2006352241A	2006-12-28
JP2011091084A	2011-05-06
JP2006313881A	2006-11-16

INABA, Yoshiyuki et al. (JP)
Yoshiyuki Inaba (JP)

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