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Title:
SEMICONDUCTOR INTEGRATED CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2003/065455
Kind Code:
A1
Abstract:
The scale of a function selector circuit is reduced by providing a controller which can change both the rise&sol fall characteristics of a signal waveform outputted from an output buffer and the logic threshold value in an input buffer in accordance with the logic level of a common node signal fed optionally. A coupling circuit includes a first transistor of depression type, thereby to lower the voltage level of a signal inputted to a second circuit and to reduce the undesired current flowing through a transistor included in the second circuit and exhibiting the GIDL characteristics. The layout of an output circuit is optimized by coupling the output buffer and the output driver through signal lines which are formed by using an upper layer where a memory cell array is formed.

Inventors:
SAITOH YOSHIKAZU (JP)
OSADA KENICHI (JP)
KIJIMA TAKEHIKO (JP)
KITAI NAOKI (JP)
Application Number:
PCT/JP2002/000742
Publication Date:
August 07, 2003
Filing Date:
January 31, 2002
Export Citation:
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Assignee:
HITACHI LTD (JP)
HITACHI ULSI SYS CO LTD (JP)
SAITOH YOSHIKAZU (JP)
OSADA KENICHI (JP)
KIJIMA TAKEHIKO (JP)
KITAI NAOKI (JP)
International Classes:
G11C7/10; (IPC1-7): H01L27/04; H01L27/10; G11C11/417
Foreign References:
JPH08125516A1996-05-17
JPH0477114A1992-03-11
JPH07202671A1995-08-04
US5952848A1999-09-14
JPH0799437A1995-04-11
JPH11204655A1999-07-30
JPS62120717A1987-06-02
US4959704A1990-09-25
JPH06334042A1994-12-02
Attorney, Agent or Firm:
Tamamura, Shizuyo (Shin Yamashiro Building 10, Kanda Ogawamachi 2-chom, Chiyoda-ku Tokyo, JP)
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