Title:
SPLIT-GATE POWER MODULE AND METHOD FOR SUPPRESSING OSCILLATION THEREIN
Document Type and Number:
WIPO Patent Application WO2003065454
Kind Code:
A3
Abstract:
The invention involves a method of packaging and interconnecting four power transistor dies to operate at a first frequency without oscillation at a second frequency higher than the first frequency but lower than a cutoff frequency of the transistors. The method comprises mounting the dies on a substrate with a lower side (drain) of each die electrically and thermally bonded to a first area of a conductive layer on the substrate; electrically connecting a source of each die to a second area of the conductive layer on the substrate; and electrically connecting a gate of each die to a third, common interior central are of the conductive layer on the substrate via separate electrical leads. The leads are sized to substantially the same electrical length and providing a first impedance corresponding to said electrical length from the common area to each gate that will pass the first frequency substantially unattenuated and providing a second impedance from the gate of one die to the gate of a second die that will substantially attenuate the second frequency. In accordance with a first embodiment, the leads take the form of one or more jumper wires in series with a film resistor. In accordance with a second embodiment, they take the form of one or more meandering striplines having predetermined impedance characteristics, and one or more gate bonding pads connected to their respective gates with long jumper wires.
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Inventors:
FREY RICHARD B
Application Number:
PCT/US2003/002326
Publication Date:
February 26, 2004
Filing Date:
January 27, 2003
Export Citation:
Assignee:
ADVANCED POWER TECHNOLOGY (US)
International Classes:
H01L21/44; H01L23/48; H01L23/66; H01L25/07; (IPC1-7): H01L25/07
Foreign References:
| US5731970A | 1998-03-24 | |||
| US4907068A | 1990-03-06 | |||
| EP0645815A2 | 1995-03-29 | |||
| DE19644009A1 | 1998-05-07 |
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