Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/163183
Kind Code:
A1
Abstract:
The purpose of the present invention is to decrease the layout size of a sense amplifier and reduce the current consumption of bit lines in a semiconductor memory device that uses a memory cell that inverts the voltage supplied during writing and the voltage detected during reading. A semiconductor memory device comprises the memory cell that is connected between the bit lines and a power source node, and a word line that is connected to a control terminal of the memory cell. Moreover, the device comprises a sense amplifier having a retaining circuit that temporarily stores data read from the memory cell, and a read-write switch that is connected between the bit lines and a first node of the retaining circuit. Furthermore, the device comprises a counter that is provided to correspond to a word line, counts the number of times the word line is activated, and outputs a data inversion control signal indicating whether the count is odd or even, and an external output circuit that performs inversion/non-inversion of data on the basis of the data inversion control signal when data in the sense amplifier retaining circuit is externally input or output.
Inventors:
TSUKADA SHUICHI (JP)
Application Number:
PCT/JP2014/059959
Publication Date:
October 09, 2014
Filing Date:
April 04, 2014
Export Citation:
Assignee:
PS4 LUXCO SARL (LU)
TSUKADA SHUICHI (JP)
TSUKADA SHUICHI (JP)
International Classes:
G11C11/36; G11C11/401; G11C11/404; H01L21/8229; H01L27/102
Foreign References:
| JP2002184172A | 2002-06-28 | |||
| JP2011070727A | 2011-04-07 | |||
| US20090213648A1 | 2009-08-27 | |||
| JP2012234940A | 2012-11-29 | |||
| US7460395B1 | 2008-12-02 | |||
| JPH1116376A | 1999-01-22 | |||
| JP2002343078A | 2002-11-29 |
Attorney, Agent or Firm:
KATO, Asamichi (JP)
Asamichi Kato (JP)
Asamichi Kato (JP)
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