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Patent Searching and Data


Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2016/136604
Kind Code:
A1
Abstract:
In this semiconductor memory device (1), without using a conventional control circuit, voltage application from a memory gate electrode (G) to a word line can be shut off by a rectifier element (3) in accordance with a voltage value applied to the memory gate electrode (G) of a memory capacitor (4) and the word line thereof. Hence, conventional switching transistors and a conventional switch control circuit for causing the switching transistors to turn on and off are unnecessary, thereby enabling downsizing. In addition, in the semiconductor memory device (1), four anti-fuse memories (2a6, 2a7, 2a10, 2a11) adjacent to each other share a single bit line contact (BC15), and for example, four anti-fuse memories (2a3, 2a4, 2a7, 2a8) adjacent to each other share a single word line contact (WC12). Hence, in comparison with a case in which an individual bit line contact and an individual word line contact are respectively provided for each anti-fuse memory, downsizing of a whole device can be accomplished.

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Inventors:
KASAI HIDEO (JP)
TANIGUCHI YASUHIRO (JP)
KAWASHIMA YASUHIKO (JP)
SAKURAI RYOTARO (JP)
SHINAGAWA YUTAKA (JP)
TOYA TATSURO (JP)
YAMAGUCHI TAKANORI (JP)
OWADA FUKUO (JP)
YOSHIDA SHINJI (JP)
HATADA TERUO (JP)
NODA TOSHIFUMI (JP)
KATO TAKAFUMI (JP)
MURATANI TETSUYA (JP)
OKUYAMA KOSUKE (JP)
Application Number:
PCT/JP2016/054809
Publication Date:
September 01, 2016
Filing Date:
February 19, 2016
Export Citation:
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Assignee:
FLOADIA CORP (JP)
International Classes:
H01L27/10
Foreign References:
JP2010087494A2010-04-15
JP2008047702A2008-02-28
JP2009147003A2009-07-02
US20130051113A12013-02-28
JP5756971B12015-07-29
Other References:
See also references of EP 3264464A4
Attorney, Agent or Firm:
YOSHIDA TADANORI (JP)
Yoshida Justice (JP)
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