Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/157724
Kind Code:
A1
Abstract:
The present invention provides a layout structure that, for mask read only memory (ROM), suppresses a reduction in operating speed without an increase in area. This semiconductor memory device comprises: word lines (31, 32) that extend in an X direction; bit lines (11, 13) that are formed in an embedded wiring layer and extend in a Y direction; and ground power supply wiring (12, 14) that extends in the Y direction. A memory cell (M00) is provided with a transistor which is provided between the bit line (11) and the ground power supply wiring (12), a gate of which is connected to the word line (31), and a drain of which is connected to the bit line (11). Data is stored via the presence or absence of a connection between a source of the transistor and the ground power supply wiring (12).
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Inventors:
SAKAI YASUMITSU (JP)
Application Number:
PCT/JP2023/004041
Publication Date:
August 24, 2023
Filing Date:
February 07, 2023
Export Citation:
Assignee:
SOCIONEXT INC (JP)
International Classes:
G11C17/12; H10B20/00
Domestic Patent References:
| WO2020230665A1 | 2020-11-19 | |||
| WO2019220983A1 | 2019-11-21 | |||
| WO2020230666A1 | 2020-11-19 |
Foreign References:
| JP2001511308A | 2001-08-07 | |||
| JP2000340681A | 2000-12-08 |
Attorney, Agent or Firm:
MAEDA & PARTNERS (JP)
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