Title:
SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
WIPO Patent Application WO/2023/181172
Kind Code:
A1
Abstract:
According to the present invention, there is a p layer 1 that is a semiconductor matrix, there is an n+ layer 2 that extends to one side, there is a second impurity layer n+ layer 3 that is in contact with the p layer 1 on the side opposite from the n+ layer 2, there is a first gate conductor layer 5 that coats portions of the p layer 1 and the n+ layer 2 with a first gate insulating layer 4 and is in contact with the first gate insulating layer 4, there is a second gate conductor layer 7 that coats portions of the p layer 1 and the n+ layer 3 with a second gate insulating layer 6 and is electrically separated from the gate electrode 5, and voltages are respectively applied to the n+ layer 2, the n+ layer 3, and the gate conductor layers 5 and 7 to enable memory operations. The present invention is characterized in that the gate capacitance per unit area of a MOS structure formed at that time with the gate conductor layer 7, the gate insulating layer 6, and the p layer 1 is smaller than that of a MOS structure formed with the gate conductor layer 5, the gate insulating layer 4, and the p layer 1.
Inventors:
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
Application Number:
PCT/JP2022/013515
Publication Date:
September 28, 2023
Filing Date:
March 23, 2022
Export Citation:
Assignee:
UNISANTIS ELECT SINGAPORE PTE (SG)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
KAKUMU MASAKAZU (JP)
SAKUI KOJI (JP)
HARADA NOZOMU (JP)
International Classes:
H01L21/336; H01L27/105; H01L29/788; H01L29/792
Foreign References:
| US20200135863A1 | 2020-04-30 | |||
| JP2009252264A | 2009-10-29 | |||
| JP2003188279A | 2003-07-04 | |||
| JP2008147514A | 2008-06-26 |
Attorney, Agent or Firm:
TANAKA Shinichiro et al. (JP)
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