SEMICONDUCTOR WAFER AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

WIPO Patent Application WO2010110233

A1

Provided is a semiconductor wafer wherein regions to be a plurality of chips can be tested in parallel at a high speed. A semiconductor device manufacturing method wherein the above-mentioned semiconductor wafer is used in the intermediate step is also provided. In the semiconductor wafer, the regions to be the plurality of semiconductor chips are disposed in columns and rows with dicing lines between the regions. The semiconductor wafer is provided with: a plurality of pads for inspection, which are disposed in a region between the semiconductor chips, including the dicing lines of the semiconductor wafer; wiring between the pads for inspection, which is disposed in parallel to the pads in the region between the semiconductor chips and connects between the pads; and wiring between chips, which connects at least two regions among the regions to be the semiconductor chips. The wiring between the pads for inspection and the wiring between the chips are electrically connected to each other.

NAKAGAWA YOSHIHIRO (JP)
NOSE KOICHI (JP)
NOGUCHI KOICHIRO (JP)
TAGO MASAMOTO (JP)
UCHIDA SHINICHI (JP)
SATO YOSHIYUKI (JP)

PCT/JP2010/054918

September 30, 2010

March 23, 2010

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NEC CORP (JP)
RENESAS ELECTRONICS CORP (JP)
NAKAGAWA YOSHIHIRO (JP)
NOSE KOICHI (JP)
NOGUCHI KOICHIRO (JP)
TAGO MASAMOTO (JP)
UCHIDA SHINICHI (JP)
SATO YOSHIYUKI (JP)

H01L21/66; H01L21/3205; H01L23/52

JP2001313318A	2001-11-09
JPH11330176A	1999-11-30
JP2007165577A	2007-06-28

KATO, Asamichi (JP)
Asamichi Kato (JP)

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