Title:
SENSE AMPLIFICATION STRUCTURE AND MEMORY ARCHITECTURE
Document Type and Number:
WIPO Patent Application WO/2023/024608
Kind Code:
A1
Abstract:
The present disclosure provides a sense amplification structure and a memory architecture, comprising: a first PMOS transistor, a gate electrode being connected to a second complementary sense bit line, and a source electrode being connected to a first signal terminal; a first NMOS transistor, a gate electrode being connected to an initial bit line, a drain electrode of the first PMOS transistor and a drain electrode of the first NMOS transistor connected to a first complementary sense bit line; a second PMOS transistor, a gate electrode being connected to a second complementary sense bit line; a second NMOS transistor, a gate electrode being connected to an initial complementary bit line, a source electrode being connected to a second signal terminal, and a drain electrode of the second PMOS transistor and a drain electrode of the second NMOS transistor being connected to the first complementary sense bit line; an offset cancellation module connecting the initial bit line and the first complementary sense bit line, and connecting the initial complementary bit line and a first sense bit line; and a control module connecting a second sense bit line and the second complementary sense bit line, and used to supply a bias voltage to the first PMOS transistor and the second PMOS transistor according to a control signal.
Inventors:
CHI SUNGSOO (CN)
Application Number:
PCT/CN2022/094359
Publication Date:
March 02, 2023
Filing Date:
May 23, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C11/4091; G11C11/4097
Foreign References:
| CN112767975A | 2021-05-07 | |||
| CN112712837A | 2021-04-27 | |||
| US20150357021A1 | 2015-12-10 |
Attorney, Agent or Firm:
BOXIN CHINA INTELLECTUAL PROPERTY (CN)
Download PDF: