Title:
SEQUENTIAL LEAST SQUARES-BASED CONSISTENT CLOCK SYNCHRONIZATION FREQUENCY DEVIATION ESTIMATION METHOD
Document Type and Number:
WIPO Patent Application WO/2022/236916
Kind Code:
A1
Abstract:
A sequential least squares-based consistent clock synchronization frequency deviation estimation method, relating to the technical field of wireless sensor networks. According to the method, for a random bounded communication delay scene in compliance with an arbitrary distribution, a relational model for clock information and delays between nodes is established; by fully considering all clock information received by the nodes from respective neighbors, a clock parameter estimation model and a principle of least squares-based cost function are constructed; a relative clock frequency deviation between the nodes is iteratively estimated by using a sequential least squares method; and logic clock parameters of the nodes are updated by using a consistent clock synchronization method, such that all the nodes in a network achieve global clock consistency in a fully distributed manner. The method improves the accuracy of relative frequency deviation estimation, effectively reduces storage overhead of nodes, and improves the robustness of a consistent synchronization algorithm for communication delays.
Inventors:
WANG HENG (CN)
GONG PENGFEI (CN)
WANG PING (CN)
GONG PENGFEI (CN)
WANG PING (CN)
Application Number:
PCT/CN2021/099979
Publication Date:
November 17, 2022
Filing Date:
June 15, 2021
Export Citation:
Assignee:
UNIV CHONGQING POSTS & TELECOM (CN)
International Classes:
H04W56/00
Foreign References:
| CN110505683A | 2019-11-26 | |||
| CN111416785A | 2020-07-14 | |||
| US20180041329A1 | 2018-02-08 | |||
| US20150092640A1 | 2015-04-02 |
Attorney, Agent or Firm:
TIDYTEND INTELLECTUAL PROPERTY LAW FIRM (CN)
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