TECHNICAL FIELD Various embodiments relate to a die comprising a substrate and a plurality of cells arranged adjacent to each other, wherein the plurality of cells are all of the same size and all comprise the same integrated circuit. Various embodiments relate to a method of preparing the plurality of cells. BACKGROUND

Space on wafers for preparation of integrated circuits is costly. Further, with a reduction of the transistor size, the cost per logic element also increases. Further, design, layout, and preparation of masks and masks sets used for exposing resist films during the preparation of integrated circuits is also costly.

SUMMARY

Therefore, a need exists for techniques which allow for a reduction of costs associated with the preparation of integrated circuits.

This need is met by the features of the independent claims. The dependent claims define embodiments. According to various embodiments, a die is provided. The die comprises a substrate and a plurality of cells. The plurality of cells are arranged adjacent to each other on the substrate. The plurality of cells are all of the same size and all comprise the same integrated circuit. According to various embodiments, a method is provided. The method comprises preparing a plurality of cells arranged adjacent to each other on a substrate of a wafer. The plurality of cells are of the same size and all includes the same integrated circuit. It is to be understood that the features mentioned above and features yet to be explained below can be used not only in the respective combinations indicated, but also in other combinations or in isolation, without departing from the scope of the present invention. Features of the above-mentioned aspects and embodiments may be combined with each other in other embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and additional features and effects of the invention will become apparent from the following detailed description when read in conjunction with the accompanying drawings, in which like reference numerals refer to like elements.

FIG. 1 schematically illustrates a cell arranged on a substrate of a die according to various embodiments, wherein the cell comprises an integrated circuit and metal wires connecting electrical contacts arranged on opposing edges of the substrate.

FIG. 2 schematically illustrates a cell arranged on a substrate of a die according to various embodiments, wherein the cell comprises an integrated circuit and metal wires connecting electrical contacts arranged on opposing edges of the substrate.

FIG. 3 is a side view of a die comprising a substrate and a cell arranged on the substrate, wherein the cell is formed by a plurality of stacked layers and a metal layer.

FIG. 4 is a schematic illustration of a die comprising a plurality of cells in a matrix arrangement having a single column and four rows and further comprising shared logic according to various embodiments, wherein each cell comprises an integrated circuit configured to communicate with the shared logic via a daisy chain communication implemented by the plurality of integrated circuits, wherein at least some edges of the cells extend to an edge of the substrate.

FIG. 5 is a schematic illustration of a die comprising a plurality of cells in a matrix arrangement having a two columns and four rows and further comprising shared logic according to various embodiments, wherein each cell comprises an integrated circuit configured to communicate with the shared logic via a daisy chain communication implemented by the plurality of integrated circuits, wherein at least some edges of the cells extend to an edge of the substrate.

FIG. 6 is a schematic illustration of a wafer comprising a plurality of cells and a plurality of shared logic prior to slicing the wafer according to a slicing concept to create multiple dies.

FIG. 7 generally corresponds to FIG. 6 and schematically illustrates a first slicing concept for the wafer of FIG. 6 according to various embodiments, the first slicing concept facilitating fabrication of a first device type where each created die comprises a single cell.

FIG. 8 generally corresponds to FIG. 6 and schematically illustrates a second slicing concept for the wafer of FIG. 6 according to various embodiments, the second slicing concept facilitating fabrication of a second device type which is different from the first device type of FIG. 7, wherein each created die comprises four cells and a shared logic.

FIG. 9 schematically illustrates the integrated circuit of a cell according to various embodiments. FIG. 10 schematically illustrates the shared logic according to various embodiments. FIG. 1 1 schematically illustrates a first device type being a G.fast Customer Premises Equipment transceiver comprising a die having a single cell and no shared logic, and further schematically illustrates a second device type being a G.fast Central Office transceiver comprising a die having a plurality of cells and shared logic.

FIG. 12 is a schematic illustration an arrangement of multiple positions of a mask on a wafer for stitched exposure according to various embodiments, wherein the positions of the mask result in preparation of the shared logic.

FIG. 13 is a schematic illustration an arrangement of multiple positions of a mask on a wafer for stitched exposure according to various embodiments, wherein the positions of the mask result in suppressed preparation of the shared logic. FIG. 14 is a schematic illustration an arrangement of multiple positions of a mask on a wafer for stitched exposure according to various embodiments, wherein the positions of the mask result in preparation of waste area instead of the shared logic.

FIG. 15 is a flowchart of a method according to various embodiments.

FIG. 16 is a flowchart of a method according to various embodiments. FIG. 17 is a flowchart of a method according to various embodiments. FIG. 18 is a flowchart of a method according to various embodiments. FIG. 19 is a flowchart of a method according to various embodiments. DETAILED DESCRIPTION OF EMBODIMENTS

In the following, embodiments of the invention will be described in detail with reference to the accompanying drawings. It is to be understood that the following description of embodiments is not to be taken in a limiting sense. The scope of the invention is not intended to be limited by the embodiments described hereinafter or by the drawings, which are taken to be illustrative only.

The drawings are to be regarded as being schematic representations and elements illustrated in the drawings are not necessarily shown to scale. Rather, the various elements are represented such that their function and general purpose become apparent to a person skilled in the art. Any connection or coupling between functional blocks, devices, components, or other physical or functional units shown in the drawings or described herein may also be implemented by an indirect connection or coupling. A coupling between components may also be established over a wireless connection. Functional blocks may be implemented in hardware, firmware, software, or a combination thereof.

Hereinafter, slicing concepts for a wafer are disclosed. A slicing concept defines the selected scribe lines along which a wafer is sliced / cut / sawed into dies / chips. Different slicing concepts can create dies of different size.

The slicing concepts disclosed herein are based on the finding that integrated circuits (ICs) prepared on the wafer can be reused for different devices / products with minor adaptations. In particular, the slicing concepts are based on the finding that differentiation between different devices fabricated from the thus created dies can be achieved by implementing different slicing concepts of the wafer. By reusing the ICs for different devices, the cost per device can be reduced. In some examples, the techniques disclosed herein may be applied to transceiver devices employed in communication systems. Examples include transceiver devices employed for Internet of Things (loT) application. Here, due to the large number of devices, a flexibility in selection of the type of the device and a reduction of costs per device can be desirable. Examples of transceivers include, but are not limited to: transceivers operating according to the International Telecommunications Union (ITU) Telecommunications standard (ITU-T) G.9701 G.fast protocol, the ITU-T G.992.X (ADSL and ADSL 2+), G.993.1 (VDSL1 ), and G.993.2 (VDSL2). Respective techniques may also be applied to non-DSL transceivers; examples include the Institute of Electrical and Electronics Engineers (IEEE) 802.1 1 Wireless Local Area Network (WLAN) communication protocol and the Third Generation Partnership Project (3GPP) Long- Term Evolution (LTE) or Universal Mobile Telecommunications system (UMTS) protocol. Further examples include Bluetooth and satellite communication. Such transceiver devices of modern communication systems often comprise multiple transceiver stages for communicating on different channels. E.g., different channels may be associated with different users or may be employed to communicate with a single user according to Multiple Input Multiple Output (MIMO) techniques. Different transceiver devices may thus be differentiated from each other based on a number of channels.

The techniques disclosed herein are not limited to devices relating to transceivers employed in communication systems. The techniques herein may be readily applied, e.g., to all kinds and types of devices which rely on a certain number of cells employing the same logic.

In some examples, a die comprises a substrate and a plurality of cells. The plurality of cells are arranged adjacent to each other on the substrate. The plurality of cells are all of the same size and all comprise the same IC. E.g., the ICs of the plurality of cells can implement the same logic; one example would be that the ICs of the plurality of cells all implement Digital Frontends (DFE) and/or Analog Frontends (AFE) of transceivers. Thus, in some examples, the plurality of cells may all be identical to each other.

By using the plurality of cells being all of the same size and all comprising the same IC, easy differentiation between different devices may be achieved by slicing a corresponding wafer according to different slicing concepts to comprise different numbers of the cells, depending on the particular device. E.g., for a first device type, the die may comprise a single cell; while for a second device type, the die may comprise 2, 4, or 8 cells.

Thus, in some examples, the plurality of cells are arranged adjacent to each other on the substrate of the wafer; further, a plurality of scribe lines delimiting the plurality of cells from each other is prepared. At least some of the plurality of scribe lines may be selected for slicing the wafer to create the at least one die. Said selecting of scribe lines may depend on the type of the device which is fabricated, e.g., by packaging the corresponding die.

Thus, the cells may be seen as the basic building blocks for fabrication of various devices. The cells for different devices may be designed highly redundant such that it is possible to fabricate different products using the same basic building blocks, e.g., with minor adaptations to the design of the cells and / or the preparation process including slicing.

FIG. 1 illustrates aspects of a cell 101 that is arranged on a substrate 190. The cell 101 can be a basic building block for a device to be fabricated. The device may comprise a single cell 101 or a plurality of cells 101 .

The cell 101 comprises an IC 1 1 1. The IC 1 1 1 may comprise digital logic elements and/or analog logic elements (not shown in FIG. 1 ). E.g., the IC 1 1 1 may comprise elements selected from the group comprising: a processor; a non-volatile memory; a baseband chip; an analog-to-digital converter; a digital-to-analog converter; an AFE; a DFE; etc. Depending on the kind and type of device to be fabricated from the cell 101 , the elements and the configuration of the IC 1 1 1 may vary. In some examples, the IC 1 1 1 may comprise a large number of logic elements, e.g., more than 100.000 logic elements, preferably more than 1.000.000 logic elements, more preferably more than 10.000.000 logic elements.

The cell 101 further comprises electrical contacts 126 arranged at opposing sides 101 A, 101 B of the cell 101. In the example of FIG. 1 , the electrical contacts 126 are coupled via metal wires forming circuitry 127 with the IC 1 1 1. The electrical contacts 126 are configured to electrically connect adjacent cells 101 (in FIG. 1 only a single cell 101 is shown). E.g., the electrical contacts 126 may be configured to support data communication in-between ICs 1 1 1 of adjacent cells 101. The electrical contacts 126 may alternatively or additionally be configured to support data communication in- between the ICs 1 1 1 of various cells 101 and further elements such as shared logic. E.g., for connecting the electrical contacts 126 between neighboring cells 101 corresponding metal wires may be provided (not shown in FIG. 1 ). Provisioning the electrical contacts 126 may facilitate communication of the IC 1 1 1 with adjacent ICs and/or shared logic.

FIG. 2 illustrates aspects of a cell 101 that is arranged on a substrate 190 according to various examples. FIG. 2 generally corresponds to FIG. 1. However, in FIG. 2, the electrical contacts 126 arranged at the opposing sides 101 A, 101 B are not interconnected via the IC 1 1 1 ; rather, the circuitry 127 is routed on the substrate 190 around the IC 1 1 1. Thereby, the electrical contacts 126 may facilitate direct communication of adjacent cells 101 arranged next to the sides 101 A, 101 B.

As illustrated in FIG. 2, it is possible that the IC 1 1 1 is coupled with at least one of the electrical contacts 126. Such a coupling may facilitate communication of the IC 1 1 1 with adjacent ICs and/or shared logic. The ICs 1 1 1 of the dies 101 according to the examples of FIGs. 1 and 2 may be prepared using common fabrication techniques, e.g., employing Complementary Metal- Oxide-Semiconductor (CMOS) technology, e.g., with gate lengths in the sub-50 nanometer regime.

While in FIGs. 1 and 2 a scenario has been shown where the electrical contacts 126 are provided at the long edges 101 A, 101 B of the substrate 190, in other examples the electrical contacts 126 may be provided, alternatively or additionally, at the short edges. It is also possible to inter-connect perpendicularly arranged edges in some examples, e.g., short and long edges. In other examples, the substrate 190 may be of square form.

Referring to FIG. 3, the cells 101 may be formed by a plurality of stacked layers 281 - 283 arranged on top of the substrate 190. The substrate 190 may be of Silicon. The stacked layers 281 - 283 may be comprise elements selected from the group comprising: metal; semiconductor; Silicone; insulators; and dopants. The various layers 281 - 283 may be deposited in sequential exposure and deposition steps using masks. Different masks of a mask set may be used for the different stacked layers 281 - 283. It is possible that the plurality of stacked layers 281 - 283 of various cells 101 arranged adjacent to each other on a die are all identical. Thereby, the same mask layout may be reused for different cells 101.

In FIG. 3, a metal layer 284 is illustrated. The metal layer 284 may be made of a noble metal such as gold, silver, etc. The metal layer 284 may be prepared using exposure and deposition. The metal layer 284 may provide a certain resistance, e.g., a 1 kOhm resistance.

While in the example of FIG. 3, the metal layer 284 is arranged on top of the further stacked layers 281 - 283, in other examples, the metal layer 284 may be arranged at a different position - e.g., underneath or sandwiched in-between - with respect to the stacked layers 281 - 283. The position of the metal layer 284 is not germane to the techniques disclosed herein. It is possible that the metal wire 284 forms the electrical contacts 126 and / or the metal wires of the circuitry 127. It is, alternatively or additionally, possible that the metal layer 284 forms a metal wire which electrically connects adjacent ones of the plurality of cells 101 with each other, e.g., via the electrical contacts 126.

In some examples, it is possible that exposure and deposition of the metal layer 284 is selectively executed depending on the type of the device to be fabricated. Hence, it is possible that differentiation between different types of devices is achieved by adapting the mask set to be used by selectively using the mask relating to the metal layer 284 depending on the type of the product. Thus, a difference between different types of devices can be the single metal layer 284 in some examples. E.g., some types of devices may not require any communication between the cells 101 and / or between the cells 101 and shared logic; here, it may not be required to provide the metal layer 284. Yet, other types of devices may require communication between the cells 101 and / or between the cells and shared logic; here, it may be required to provide the metal layer 284.

Communication between the cells 101 and between the cells 101 and shared logic is illustrated by FIG. 4. FIG. 4 illustrates aspects of an electrical interconnection 129 between multiple cells 101 - 104 of a die 191 that are all arranged on the same substrate 190. Here, the metal layer 284 forms the metal wires 125 which electrically connect adjacent ones of the plurality of cells 101 - 104, e.g., via the electrical contacts 126 and the circuitry 127 (both not shown in FIG. 4). By means of the metal wires 125, communication between adjacent cells 101 - 104 may be facilitated. In detail, the metal wires 125 may electrically connect adjacent cells 101 - 104 via adjacent electrical contacts 126 arranged next to each other on both sides of a scribe line 180. As can be seen from FIG. 4, the die 191 further comprises scribe lines 180 which delimit adjacent ones of the plurality of cells 101 - 104 from each other. The scribe lines may comprise visual features and / or structural features which facilitate slicing of a wafer. The metal wires 125 electrically connecting the adjacent ones of the plurality of cells 101 - 104 with each other cross the scribe lines 180. The scribe lines are provided in order to give an opportunity to select different slicing schemes for fabrication of different types of devices. To avoid the need of adapting the mask design for each type of device, the scribe lines are present also in types of devices where they are not actually used according to the respective slicing concept.

To give an example: As can be seen from FIG. 4, for the device to be fabricated from the illustrated die 191 , the scribe line 180 in-between, e.g., cells 102 and 103 has not been selected. For other types of devices to be fabricated, this scribe line 180 may be selected (not shown in FIG. 4).

Each cell 101 - 104 may be configured to communicate with other cells 101 - 104 and / or shared logic 120. The shared logic 120 is arranged adjacent to the cell 104. The shared logic may comprise logic which is shared between all cells 101 - 104. To access the shared logic 120, each one of the ICs 1 1 1 of the plurality of cells 101 - 104 is configured to communicate with the shared logic 120 via a daisy chain communication 129. Thereby, complexity of the individual cells may be reduced and certain logic may be outsourced from the cells 101 - 104 to the shared logic 120. An overhead can be reduced by a factor which corresponds to the number of cells communicating with the shared logic 120. This simplifies the design of each IC 1 1 1 which allows to reduce total a number of logic elements, thereby reducing complexity and costs. Further, power saving effects may be achieved, because certain processing tasks may be implemented more efficiently using the shared logic 120. E.g., the daisy chain communication 129 may be implemented by the plurality of ICs 1 1 1 , e.g., in a scenario corresponding to the architecture of FIG. 1. In other examples, the daisy chain communication 129 may be implemented by a particular routing of the circuitry 127 inter-connecting the electrical contacts 126 arranged at opposing sides 101 A, 101 B of the plurality of cells 101 - 104 (cf. FIG. 2).

To give an example: It may be possible that the IC 1 1 1 of the cell 103 receives a message from the IC 1 1 1 of the cell 102; then, the IC 1 1 1 of the cell 103 may send a further message to the cell 104. The further message and the message may both be addressed to the shared logic 120. As can be seen, the daisy chain communication 129 is implemented by a bus-like communication architecture of the cells 101 - 104 and the shared logic 120.

FIG. 4 also illustrates aspects relating to the arrangement of the plurality of cells 101 - 104 on the substrate 190 of the die 191 . In particular, the plurality of cells 101 - 104 are arranged in a matrix structure; in the example of FIG. 4, the matrix structure comprises a single column and four rows. However - referring to FIG. 5 - such a configuration of the matrix structure is exemplary only and can vary for different examples. E.g., in FIG. 5, the matrix structure comprises two columns and four rows.

FIGs. 4 and 5 also illustrates aspects with respect to the arrangement of the cells 101 - 108 with respect to edges 190A of the substrate 190. As can be seen, the cells 101 - 108 extend to the edge 190A of the substrate 190. The edges 190A formed by slicing of a wafer along respective scribe lines.

The corresponding wafer 192 is illustrated in FIG. 6. Here, a large number of cells 801 - 832 is prepared adjacent to each other on the substrate 190 of the wafer 192. Again, the cells 801 - 832 are of the same size and all include the same IC 1 1 1 (not shown in FIG. 6). E.g., the cells 801 - 804 could correspond to the cells 101 - 104 of FIG. 4; e.g., the cells 801 - 804, 809 - 812 could correspond to the cells 101 - 108 of FIG. 5. The wafer 192 also comprises the shared logic 120. Provisioning the shared logic 120 on the wafer 192 is optional. In some example, shared logic 120 is not prepared. As can be seen from FIG. 6, different scribe lines 180 are prepared on the wafer 192. The scribe lines 180 delimit the plurality of cells 801 - 832 from each other. According to different slicing concepts, different scribe lines 180 are selected for slicing of the wafer 192 along the selected scribe lines 180 to create the die 191. By preparing the scribe lines 180, a flexibility is given to select different scribe lines according to different slicing concepts. Thereby, different devices may be fabricated from the same wafer 192, depending on the slicing concept. Here, differentiation between different products can be achieved by the different slicing concepts.

FIG. 7 illustrates a first slicing concept according to various examples. According to the first slicing concept, all scribe lines 180 are selected for slicing 195 the wafer 192 (the selected scribe lines 180 are illustrated in FIG. 7 by bold dashed lines). According to the first slicing concept, each die 191 comprises a single cell 801 - 832.

E.g., in such a scenario there would be no need to prepare the metal layer 284; there are no further cells 801 - 832 or shared logic 120 on each die 191 with respect to which communication could be required.

In the example of FIG. 7, the dies comprising the shared logic 120 may be waste. FIG. 8 illustrates a second slicing concept according to various examples. According to the second slicing concept, only a fraction of the scribe lines 180 is selected for slicing 195 the wafer 192 (the selected scribe lines 180 are illustrated in FIG. 8 by bold dashed lines). In the scenario of FIG. 8, each die 191 comprises four cells 801 - 832 and shared logic 120 (cf. FIG. 4). The numbers of cells 101 - 108, 801 - 832 per die 191 is thus given by the slicing concept. The particular number of cells 101 - 108, 801 - 832 per die 191 can vary in different examples. E.g., for a first type of device there may be a first number of cells 101 - 108, 801 - 832 per die 191 , while for a second type of device there may be a second number of cells 101 - 108, 801 - 832 per die 191. The first number may be different than the second number. E.g., the first number may be one.

Depending on the particular matrix structure envisioned, different slicing concepts may be implemented for the wafer 192 of FIG. 6. Where the dies 191 created by slicing 195 according to the slicing concepts as illustrated in FIGs. 7 and 8 are packaged to obtain devices (device fabrication), different types of devices will result from the different slicing concepts of FIGs. 7 and 8. Hence, selecting of the scribe lines 180 can depend on a type of the device. To give an example: Considering a scenario where the ICs 1 1 1 of the various cells 801 - 832 implement DFEs and AFEs for communicating on a channel of a communication system, the device type obtained from the slicing concept of FIG. 7 may correspond to a single-channel transceiver; while the device type obtained from the slicing concept of FIG. 8 may correspond to a multi-channel transceiver.

FIG. 9 illustrates schematically details of the IC 1 1 1 that may be used for the various cells 101 - 108, 801 - 832. The particular design of the IC 1 1 1 is not germane for the slicing concepts. E.g., the IC 1 1 1 may comprise one or more processors 1 12 and an interface 1 13 configured to communicate with further ICs 1 1 1 , further cells 101 - 108, 801 - 832, and / or the shared logic 120. E.g., the IC 1 1 1 may comprise non-volatile memory which may store control instructions that can be executed by the processor 1 12.

FIG. 10 illustrates schematically details of the shared logic 120. The particular design of the shared logic 120 is not germane for the slicing concepts. E.g., the shared logic 120 may comprise one or more processors 121 and an interface 123. The interface 123 is configured to communicate with the ICs 1 1 1 and / or the cells 101 - 108, 801 - 832. The shared logic 120 may further comprise non-volatile memory; in some examples, it is possible that the non-volatile memory 122 stores control instructions that can be executed by the processors 1 12 of the ICs 1 1 1 of the various cells 101 - 108, 801 - 832. Further, certain tasks may be outsourced from the processors 1 12 of the ICs 1 1 1 of the various cells 101 - 108, 801 - 832 to the processor 121 of the shared logic 120.

In some examples, the shared logic 120 is thus configured to execute interfacing each one of the ICs 1 1 1 of the cells 101 - 108, 801 - 832 of the same die 191 with an external entity. Here, the shared logic 120 may operate as an interface for the ICs 1 1 1. E.g., the external entity may be a modem, a database, a server, a backbone interface; a further die; etc. In further examples, the shared logic 120 is configured to execute shared processing of tasks assigned to the processors of the ICs 1 11 of the plurality of cells 101 - 108, 801 - 832 of the same die 191. Also, the shared logic 120 may be configured to store program code of a program executed by the processors 1 12.

FIG. 1 1 illustrates an example where a first device 291 is differentiated from a second device 292 by the number of cells 101 - 104 per die 191. Hence, FIG. 1 1 illustrates how the basic building blocks of the cells 101 - 104 can be assembled differently for different products.

In the example of FIG. 1 1 , the ICs 1 1 1 of the cells 101 - 104 all implement a G.fast transceiver. In the example of FIG. 1 1 , the first type of the device 291 is a G.fast Customer Premises Equipment (CPE) device and the second type of the device 292 is a G.fast Central Office (CO) device. The CPE and CO devices 291 , 292 may implement further functionality. E.g., the CPE device 291 may comprise DRAM or FLASH memory and a WLAN or LAN interface (all not shown in FIG. 1 1 ). The far-end CPE device 291 implements a single communication channel for communication via a copper wire 299 with the CO device 292. Because of this, the CPE device 291 only requires a single cell 101 implementing, both, a DFE and an AFE. Differently, the near-end CO device 292 implements multiple channels for communication via a plurality of copper wires 299 with different far-end CPE devices 291. Also in this scenario, each cell 101 - 104 implements, both, the DFE and the AFE. Here, the DFE and AFE may implement functionality of a physical layer of the G.fast protocol stack.

In the example of FIG. 1 1 , the shared logic 120 may facilitate G.fast vectoring. For this, the shared logic 120 may implement or interface to a G.fast vectoring calculation engine for reducing crosstalk between the various channels handled by the CO device 292. Techniques of vectoring for reducing crosstalk are generally known in the art such that further details of vectoring are not required to be explained in the present context.

The shared logic 120 facilitates the vectoring calculation engine for all cells 101 - 104 on the respective die 191. As such, the shared logic 120 provides processing power to the DFE and AFE implemented by the ICs 1 1 1 of the cells 101 - 104. Further, due to the centralized concept of vectoring - accessing and modifying transmission properties of all channels - an efficient integration can be achieved due to the shared logic 120. Power consumption can be reduced. To facilitate communication between each one of the cells 101 - 104 and the shared logic 120, the metal wires 125 electrically connecting adjacent ones of the cells 101 - 104 with each other are provided. The shared logic 120 of the example of FIG. 5 may implement further functionality alternatively or additionally to facilitating the G.fast vectoring calculation engine. In the example of FIG. 1 1 , the shared logic 120 may implement, alternatively or additionally, an analog Serializer/Deserializer (SerDes) for communication; thereby, power consumption may be reduced. E.g., the shared logic 120 may comprise the non-volatile memory 122 which stores the program code that may be executed by the processors 1 12 of each one of the cells 101 - 104. E.g., the memory 122 of the shared logic 120 may store G.fast protocol program code which is executable by the DFE of each one of the ICs 1 1 1 of the plurality of cells 101 - 104. Thereby, functionality of the physical layer of the G.fast protocol stack may be implemented. As such, some of the metal wires 125 may provide an electrical connection to access the memory 122 - while others of the metal wires 125 may provide an electrical connection to access the processing power of the processor 121.

In the example of FIG. 1 1 , each one of the cells 101 - 104 is further coupled with a backbone interface 291 -1 directly (as illustrated by the horizontal double-headed arrows in FIG. 1 1 ). E.g., the backbone interface 291-1 may access an Gigabit Passive Optical Network (GPON).

FIG. 1 1 illustrates an 8-port CO modem where two dies 191 , each comprising four cells 101 - 104 (in FIG. 1 1 only the cells 101 - 104 of the first die 191 are illustrated), are connected with each other. Also interfacing between multiple dies 191 is facilitated by the shared logic 120. As such, the shared logic 120 is configured to execute interfacing of each one of the ICs 1 1 1 of the plurality of cells 101 - 104 with an external entity being the further die 191 of the multi-port CO device 292. Interfacing between the multiple dies 191 of the multi-ports CO device 292 may further facilitate crosstalk cancellation by vectoring techniques. In particular, the copper wires 299 of the two dies 191 may all share a common cable binder and thus may exhibit significant crosstalk from each other.

As illustrated in FIG. 1 1 , the shared logic 120 is provided for the CO device 292 - but is not provided for the CPE device 291. E.g., G.fast vectoring calculation functionality may not be required at the far-end CPE side. Vectoring may be executed at the near-end only. Also, interfacing between different dies 191 may not be required for the CPE device 291 only comprising a single cell 101. Because of this, it is not required to provision the shared logic 120 on the die 191 of the CPE device 291 (as illustrated in FIG. 1 1 ). Likewise, it is not required to provide the metal wires 125 on the die 191 of the CPE device 291 (as illustrated in FIG. 1 1 ).

In some examples, it is possible that - depending on the type of the device 291 , 292 which is fabricated from a wafer 192 - the corresponding metal layer 284 forming the metal wire 125 is selectively prepared. E.g., if it is intended to fabricate the CPE device 291 (CO device 291 ) from a wafer 192, a respective exposure and deposition step for forming the layer 284 and the metal wire 125 may be skipped (may be executed). E.g., if it is intended to fabricate the CPE device 291 (CO device 291 ) from a wafer 192, respective exposure and deposition steps for forming the shared logic 120 may be skipped (may be executed). In other words, preparing the shared logic 120 may be selectively executed depending on the type of the device 291 , 292.

In other examples, it is possible that the exposure and deposition step for forming the layer 284 and the metal wire 125 is executed irrespective of the type of the device 291 , 292 to be fabricated from the respective wafer 192. Here, by slicing the wafer 192 along the respective scribe lines, the metal wires 124 inter-connecting adjacent cells 101 - 108, 801 - 832 may be split in two. In some scenarios, the slicing concepts used for preparing the die 191 of the CPE device 291 may be such that the shared logic 120 is removed from the die 191. In other scenarios, the slicing concept used for preparing the die 191 of the CPE device 291 may not remove the shared logic 120 from the die 191 ; rather, the shared logic 120 may remain on the die 191 as a waste area not functionally operable.

FIG. 12 illustrates aspects with respect to mask positions 301 - 304 used for exposing the wafer 192 a plurality of times, e.g., for each one of the plurality of stacked layers 281 - 283 and the metal layer 284. Such a technique is sometimes referred to as stitching. Such techniques may be applied where the footprint of the mask is not sufficient for exposing the entire wafer 192 in a one-shot process. In particular, FIG. 12 illustrates the mask positions 301 - 304 used for exposing the wafer 192 when fabricating the CO device 292. As can be seen from FIG. 12, the entire wafer 192 is exposed using four mask positions 301 - 304 which are adjacent to each other. In particular, distances 31 1 , 312 between the adjacent mask positions 301 - 304 are illustrated in FIG. 12. Further, in FIG. 12, the length 120A of an edge of the shared logic 120 is illustrated.

FIG. 13 illustrates aspects with respect to mask positions 301 - 304 used for exposing the wafer 192 a plurality of times when fabricating the CPE device 291. As can be seen from a comparison of FIGs. 12 and 13, the distance 31 1 between the mask positions 301 - 304 differs between the exposure of the wafer 192 for the CO device 292 and the CPE device 291 by the length 120A of the shared logic 120. Thereby, the wafer 192 used for fabricating the CPE device 291 does not comprise the shared logic 120. Hence, preparing of the shared logic 120 is selectively executed depending on the type of the device 291 , 292. Waste area is avoided, thereby reducing costs.

FIG. 14 illustrates aspects with respect to mask positions 301 - 304 used for exposing the wafer 192 a plurality of times when fabricating the CPE device 291. As can be seen from a comparison of FIGs. 12 and 14, the distance 31 1 between the mask positions 301 - 304 does not differ between the exposure of the wafer 192 for the CO device 292 and the CPE device 291. Here, because the shared logic 120 is not required for the CPE device 291 , the respective space on the wafer 192 is waste area 850. FIG. 15 is a flowchart of a method according to various embodiments. At 1001 , the plurality of cells 101 - 108, 801 - 832 is prepared. Next, at 1002, a plurality of scribe lines 180 is prepared. While in FIG. 15 1001 and 1002 are shown as separate steps, it is generally possible to combine 1001 and 1002 into a single process. After 1002, optionally, slicing along selected scribe lines 180 may be executed (not shown in FIG. 15); further, optionally, the thus created dies may be packed to fabricate a device (not shown in FIG. 15).

FIG. 16 is a flowchart of a method according to various embodiments. FIG. 16 illustrates aspects with respect to preparing the plurality of cells 101 - 108, 801 - 832. For a first one of the plurality of layers 281 -284, at 101 1 , the mask is positioned above the wafer 192. E.g., depending on the footprint of the mask, a different number of exposure and deposition steps 1012, 1013 for different mask positions 301 -304 may be required. This is checked at 1014. When preparation of the first one of the plurality of layers 281 -284 is finished, at 1015, it is checked whether preparation of a further layer 281 -284 is required; if yes, then 101 1 - 1014 are re-executed for the further layer 281 -284. Different masks of a mask set can be used for the different layers 281 -284.

FIG. 17 is a flowchart of a method according to various embodiments. FIG. 17 illustrates aspects with respect to positioning the mask at the various mask positions 301 - 304. In particular, it is possible to check whether fabrication of a certain type of device is intended, 1021. Depending on the type of the device, it is possible to position the mask by moving the mask by a first distance, 1022, or a second distance, 1023. The first and second distances may differ from each other, e.g., by the length 120A of the shared logic 120. As can be seen from FIG. 17, by using different mask positions 301 - 304, it is possible to differentiate between fabrication of different types of devices 291 , 292.

FIG. 18 is a flowchart of a method according to various embodiments. FIG. 18 illustrates aspects with respect to selectively preparing certain layers 281 - 284 depending on the type of the device 291 , 292. At 1025, it is possible to check whether fabrication of a certain type of device is intended. The following steps, 1026 - 1028, are selectively executed if fabrication of a certain type of device 291 , 292 is intended. 1026 - 1028 generally correspond to 101 1 - 1013. At 1029, it is checked whether exposure and material deposition for a further layer is required. If this is the case, 1025 - 1028 are executed anew. As can be seen from FIG. 18, by using selective exposure and material deposition, it is possible to differentiate between fabrication of different types of devices 291 , 292. E.g., in some examples it is possible that exposition and material deposition is selectively executed for the metal layer 284 forming the metal wire 125 electrically connecting adjacent cells 101 - 108, 801 - 832, depending on the type of the device 291 , 292. In particular, it may not be required to execute exposure and material deposition for the metal layer 284 where a type of device 291 , 292 is fabricated where electrical interconnection and/or communication between a plurality of cells 101 - 108, 801 - 832 is not required. This may be the case, e.g., where dies 191 obtained by slicing from the wafer 192 only comprise a single cell 101 - 108, 801 - 832.

FIG. 19 is a flowchart of a method according to various embodiments. FIG. 19 illustrates aspects with respect to selecting different scribe lines 180 depending on the type of the device 291 , 292. At 1032, it is possible to check whether fabrication of a certain type of device is intended. Depending on the type of device 291 , 292 fabrication of which is intended, different sets of scribe lines 180 are selected, 1033, 1034. Then, slicing is executed along the selected set of scribe lines 180, 1035. As can be seen from FIG. 19, by using different slicing concepts, it is possible to differentiate between fabrication of different types of devices 291 , 292.

Thus, as can be seen from a comparison of FIGs. 17, 18, and 19, different techniques are available for differentiating between fabrication of different types of devices 291 , 292. These techniques comprise: selective exposure and material deposition for certain layers 281 - 284; employing different mask positions 301 - 304; and employing different slicing concepts. In the various examples disclosed herein, it is possible to rely on different combinations of these techniques. E.g., in some examples, differentiation between fabrication of different types of devices 291 , 292 may be achieved solely by employing different slicing concepts. In further examples, the differentiation between fabrication of different types of devices 291 , 292 may be achieved by employing a combination of different slicing concepts and mask positions 301 - 304, possibly supplemented by selective exposure and material deposition.

Summarizing, above techniques are disclosed which enable to reuse mask design and fabrication technology for different types of devices. This is achieved by assembling different types of devices from the same basic building blocks in the form of cells which are all of the same size and all comprise the same IC. Different types of devices may comprise a different number of cells.

In order to increase the flexibility in the design of the devices, the cells may be configured such that communication between each one of the cells and/or each one of the cells and the shared logic is possible. This may be achieved by a daisy chain communication supported by ICs of the cells and/or suitable circuitry inter-connecting electrical contacts arranged on opposing sides of the cells.

Shared logic may be provided for some types of devices. The shared logic can be used for different tasks; e.g., interfacing, shared processing, and/or central storage for the plurality of cells on a die may be provided by the shared logic.

In some examples, different types of devices are merely differentiated from each other by the number and/or arrangement of the plurality of cells on the corresponding die; such a scenario may correspond to only selecting different slicing concepts, but preparing all cells alike for different devices beyond that. Alternatively or additionally, it is also possible to differentiate different types of devices from each other by using selective exposure and material deposition for certain layers and/or employing different mask positions depending on the type of the device.

Although the invention has been shown and described with respect to certain preferred embodiments, equivalents and modifications will occur to others skilled in the art upon the reading and understanding of the specification. The present invention includes all such equivalents and modifications and is limited only by the scope of the appended claims.