Title:
SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS
Document Type and Number:
WIPO Patent Application WO/2018/186193
Kind Code:
A1
Abstract:
[Problem] To further improve the performance of a solid-state imaging device. [Solution] Provided is a solid-state imaging device configured by laminating, in the stated order: a first substrate having a first semiconductor substrate on which a pixel unit in which pixels are arranged is formed, and a first multilayer wiring layer laminated on the first semiconductor substrate; a second substrate having a second semiconductor substrate on which a circuit having a prescribed function is formed, and a second multilayer wiring layer laminated on the second semiconductor substrate; and a third substrate having a third semiconductor substrate on which a circuit having a prescribed function is formed, and a third multilayer wiring layer laminated on the third semiconductor substrate. The first substrate and the second substrate are affixed so that the first multilayer wiring layer and the second multilayer wiring layer face each other. A first connection structure for electrically connecting at least two of the first substrate, the second substrate, and the third substrate includes a via. The via has: a structure in which an electroconductive material is embedded in one through-hole provided so as to expose a prescribed wire in the second multilayer wiring layer while exposing a part of a prescribed wire in the first multilayer wiring layer from the reverse-surface side of the first substrate, or one through-hole provided so as to expose a prescribed wire in the third multilayer wiring layer while exposing a part of a prescribed wire in the first multilayer wiring layer or the second multilayer wiring layer from the reverse-surface side of the first substrate; or a structure in which a film of an electroconductive material is formed on the inner wall of the through-hole.
Inventors:
IIJIMA TADASHI (JP)
KAMESHIMA TAKATOSHI (JP)
MITSUHASHI IKUE (JP)
HORIKOSHI HIROSHI (JP)
HASHIGUCHI HIDETO (JP)
SHOHJI REIJIROH (JP)
ISHIDA MINORU (JP)
HANEDA MASAKI (JP)
KAMESHIMA TAKATOSHI (JP)
MITSUHASHI IKUE (JP)
HORIKOSHI HIROSHI (JP)
HASHIGUCHI HIDETO (JP)
SHOHJI REIJIROH (JP)
ISHIDA MINORU (JP)
HANEDA MASAKI (JP)
Application Number:
PCT/JP2018/011566
Publication Date:
October 11, 2018
Filing Date:
March 23, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/146; H01L21/02; H01L21/3205; H01L21/768; H01L23/522; H01L25/065; H01L25/07; H01L25/18; H04N5/369
Foreign References:
| JP2014099582A | 2014-05-29 | |||
| JP2015135938A | 2015-07-27 | |||
| JP2016171297A | 2016-09-23 |
Attorney, Agent or Firm:
KAMEYA, Yoshiaki et al. (JP)
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