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Title:
SUBSTRATE HAVING INTEGRATED SEMICONDUCTOR ELEMENT, AND MANUFACTURING METHOD FOR SAME
Document Type and Number:
WIPO Patent Application WO/2011/114774
Kind Code:
A1
Abstract:
Disclosed is a substrate which has an integrated semiconductor element, and which contains: a semiconductor element; a chip component; a peripheral insulation later which covers at least the outer peripheral surface of the semiconductor element and the chip component; upper surface-side wiring which is provided on the upper surface side of the substrate; and lower surface-side wiring which is provided on the lower surface side of the substrate. The integrated semiconductor element has a terminal on the upper surface side thereof, and the terminal is electrically connected to the upper surface-side wiring. The integrated chip component has: an upper surface-side terminal which is electrically connected to the upper surface-side wiring; a lower surface-side terminal which is electrically connected to the lower surface-side wiring; and a through-silicon via which passes through the chip component and which connects the upper surface-side terminal and lower surface-side terminal thereof.

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Inventors:
MORI KENTARO (JP)
YAMAMICHI SHINTARO (JP)
MURAI HIDEYA (JP)
KIKUCHI KATSUMI (JP)
NAKASHIMA YOSHIKI (JP)
OHSHIMA DAISUKE (JP)
Application Number:
PCT/JP2011/051295
Publication Date:
September 22, 2011
Filing Date:
January 25, 2011
Export Citation:
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Assignee:
NEC CORP (JP)
MORI KENTARO (JP)
YAMAMICHI SHINTARO (JP)
MURAI HIDEYA (JP)
KIKUCHI KATSUMI (JP)
NAKASHIMA YOSHIKI (JP)
OHSHIMA DAISUKE (JP)
International Classes:
H05K3/46; H01L23/12; H05K1/11; H05K1/18
Domestic Patent References:
WO2010024233A12010-03-04
Foreign References:
JPH0418787A1992-01-22
JP2005285945A2005-10-13
JP2010021368A2010-01-28
Attorney, Agent or Firm:
MIYAZAKI, Teruo et al. (JP)
Akio Miyazaki (JP)
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Claims:



 
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