Title:
SUBSTRATE WIRING METHOD AND SEMICONDUCTOR MANUFACTURING DEVICE
Document Type and Number:
WIPO Patent Application WO/2011/111524
Kind Code:
A1
Abstract:
The disclosed substrate wiring method can embed copper all the way to the lowest parts of a wiring pattern formed on a substrate. Said method is used to wire a substrate inside a processing vessel (100) kept in a vacuum state, said substrate having a wiring pattern formed thereon. Said method is characterized by the inclusion of: a preprocess in which a desired cleaning gas is used to clean the wiring pattern on the wafer; and an embedding step, after the preprocess, in which a clustered metal gas (metal gas clusters (Cg)) is used to embed metal nanoparticles inside the wiring pattern.
More Like This:
| JPH1027798 | WIRING FORMATION METHOD OF SEMICONDUCTOR DEVICE |
| JP3287346 | SEMICONDUCTOR DEVICE |
| JP2007266637 | ELECTRONIC DEVICE |
Inventors:
HOSHINO SATOHIKO (JP)
MATSUI HIDEFUMI (JP)
NARUSHIMA MASAKI (JP)
MATSUI HIDEFUMI (JP)
NARUSHIMA MASAKI (JP)
Application Number:
PCT/JP2011/053893
Publication Date:
September 15, 2011
Filing Date:
February 23, 2011
Export Citation:
Assignee:
TOKYO ELECTRON LTD (JP)
IWATANI CORP (JP)
HOSHINO SATOHIKO (JP)
MATSUI HIDEFUMI (JP)
NARUSHIMA MASAKI (JP)
IWATANI CORP (JP)
HOSHINO SATOHIKO (JP)
MATSUI HIDEFUMI (JP)
NARUSHIMA MASAKI (JP)
International Classes:
H01L21/3205; C23C14/32; H01L21/28; H01L21/285; H01L23/52
Foreign References:
| JP2002305161A | 2002-10-18 | |||
| JP2002305163A | 2002-10-18 | |||
| JP2000100749A | 2000-04-07 | |||
| JP2010225614A | 2010-10-07 | |||
| JP2009027157A | 2009-02-05 | |||
| JPH065544A | 1994-01-14 |
Attorney, Agent or Firm:
KAMEYA, Yoshiaki et al. (JP)
Yoshiaki Kameya (JP)
Yoshiaki Kameya (JP)
Download PDF:
Claims: