Title:
SUCCESSIVE APPROXIMATION A/D CONVERTER
Document Type and Number:
WIPO Patent Application WO/2016/203522
Kind Code:
A1
Abstract:
Provided is a successive approximation A/D converter capable of securing the full scale range of a digital signal even if the capacitance value of a capacitance circuit changes. The successive approximation A/D converter is provided with: a sampling circuit (110) that samples one pair of analog signals forming differential input signals; and capacitance circuits (121) that include attenuation capacity units (CHP, CHN) and binary capacitance units (C0P-C7P, C0N-C7N), and that reflect the signal level of a reference signal to the pair of analog signals via the attenuation capacity units (CHP, CHN) and the binary capacitance units (C0P-C7P, C0N-C7N), thereby generating a pair of voltage signals. The attenuation capacity units (CHP, CHN) each include a fixed capacity section connected between a predetermined potential node and a signal node at which the sampled analog signals are held, and a variable capacity section connected in parallel to the fixed capacity section.
Inventors:
HIRAIDE SHUZO (JP)
Application Number:
PCT/JP2015/067173
Publication Date:
December 22, 2016
Filing Date:
June 15, 2015
Export Citation:
Assignee:
OLYMPUS CORP (JP)
International Classes:
H03M1/10; H03M1/38; H03M1/26
Foreign References:
| JP2013168870A | 2013-08-29 | |||
| JP2010045723A | 2010-02-25 | |||
| US20110057823A1 | 2011-03-10 |
Attorney, Agent or Firm:
TANAI Sumio et al. (JP)
Sumio Tanai (JP)
Sumio Tanai (JP)
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