Title:
TAPE FOR SEMICONDUCTOR PROCESSING
Document Type and Number:
WIPO Patent Application WO/2017/110202
Kind Code:
A1
Abstract:
A tape for semiconductor processing is provided which enables excellent singulation of semiconductor wafers during dicing and which enables preventing package cracking during packaging. This semiconductor processing tape 10 is characterized by comprising: a dicing tape 13 comprising a substrate film 11 and an adhesive layer 12; a metal layer 14 provided on the adhesive layer 12 to protect the back surface of the semiconductor chip; and an adhesive layer 15 provided on the metal layer 14 to adhere the metal layer 14 to the back surface of the semiconductor chip, wherein the surface roughness RzJIS of the metal layer 14, based on the 10-point mean roughness, is greater than or equal to 0.5 μm and less than 10.0 μm.
Inventors:
AOYAMA MASAMI (JP)
SANO TORU (JP)
SANO TORU (JP)
Application Number:
PCT/JP2016/079626
Publication Date:
June 29, 2017
Filing Date:
October 05, 2016
Export Citation:
Assignee:
FURUKAWA ELECTRIC CO LTD (JP)
International Classes:
B32B15/08; C09J7/20; C09J11/04; C09J11/06; C09J133/06; C09J163/00; C09J171/12; C09J175/14; H01L21/301
Foreign References:
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| JP2003298230A | 2003-10-17 | |||
| JP2006103108A | 2006-04-20 | |||
| JP2000071387A | 2000-03-07 | |||
| JP2008045011A | 2008-02-28 | |||
| JP2010185013A | 2010-08-26 | |||
| JP2015185584A | 2015-10-22 | |||
| JP2013235962A | 2013-11-21 | |||
| JP2015043383A | 2015-03-05 | |||
| JP2010225651A | 2010-10-07 | |||
| JPH1167699A | 1999-03-09 | |||
| JP2012028397A | 2012-02-09 |
Attorney, Agent or Firm:
MATSUSHITA, Makoto et al. (JP)
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