TERMINAL CIRCUIT, SEMICONDUCTOR DEVICE, AND TESTING SYSTEM

Title:

TERMINAL CIRCUIT, SEMICONDUCTOR DEVICE, AND TESTING SYSTEM

Document Type and Number:

WIPO Patent Application WO/2012/123990

Kind Code:

A1

Abstract:

A terminal circuit comprises a pMOS transistor, an inductor, and a capacitor. The source of the pMOS transistor is connected to a signal terminal which either outputs, or receives as input, a transmission signal, the drain thereof is connected to a ground wire, and a control signal is received with the gate. The pMOS transistor is on when a function of rectifying characteristic impedance is active and off when the rectifying function is inactive. The inductor and the capacitor are connected to the signal terminal in order to rectify the characteristic impedance. Either switching the pMOS transistor on or off via the control signal allows switching the characteristic impedance rectifying function by the terminal circuit to either active or inactive. It is thus possible, for example, to implement a state wherein a terminal resistor is in place and monitor a signal level of a transmission signal at an output terminal without connecting an external terminal resistor.

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Inventors:

SUZUKI TOSHIHIDE (JP)
KAWANO YOICHI (JP)

Application Number:

PCT/JP2011/001540

Publication Date:

September 20, 2012

Filing Date:

March 16, 2011

Export Citation:

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Assignee:

FUJITSU LTD (JP)
SUZUKI TOSHIHIDE (JP)
KAWANO YOICHI (JP)

International Classes:

H03H11/28; G01R31/28; H03H7/38; H03K19/0175; H04B1/04; H04B3/02

Foreign References:

JP2008035165A	2008-02-14
JPH1141121A	1999-02-12
JPH08293778A	1996-11-05
JP2002344300A	2002-11-29
JP2006135344A	2006-05-25
JPH01206277A	1989-08-18
JPH06125261A	1994-05-06

Other References: