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Patent Searching and Data


Title:
TEST CIRCUIT, TEST METHOD AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/206657
Kind Code:
A1
Abstract:
A test circuit (400), a test method, and a memory. The test circuit (400) comprises: a first integrating circuit (401) used for receiving a first test signal (Test1) and configured to integrate the first test signal (Test1) to output a first integrated signal (FltNdT); a second integrating circuit (402) used for receiving a second test signal (Test2) and configured to integrate the second test signal (Test2) to output a second integrated signal (FltNdC), wherein the first test signal (Test1) and the second test signal (Test2) are inversion signals, the voltage value of the first integrated signal (FltNdT) is the product of the duty ratio of the first test signal (Test1) and the power supply amplitude, and the voltage value of the second integrated signal (FltNdC) is the product of the duty ratio of the second test signal (Test2) and the power supply amplitude; and a comparison circuit (403) connected to the first integrating circuit (401) and the second integrating circuit (402) and used for outputting a high-level signal when the first integrated signal (FltNdT) is greater than the second integrated signal (FltNdC), and outputting a low-level signal when the second integrated signal (FltNdC) is greater than the first integrated signal (FltNdT).

Inventors:
QIN JIANYONG (CN)
LI JIANNI (CN)
LIU ZHONGLAI (CN)
Application Number:
PCT/CN2022/093712
Publication Date:
November 02, 2023
Filing Date:
May 19, 2022
Export Citation:
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Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/56; G11C29/54
Foreign References:
CN114420187A2022-04-29
CN215773547U2022-02-08
CN112420113A2021-02-26
CN106233150A2016-12-14
CN107153138A2017-09-12
CN113764028A2021-12-07
US20110181308A12011-07-28
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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