Title:
TEST METHOD, TEST STRUCTURE, AND MEMORY
Document Type and Number:
WIPO Patent Application WO/2023/245780
Kind Code:
A1
Abstract:
Embodiments of the present disclosure relate to the field of semiconductor testing, and in particular to a test method, a test structure, and a memory. The test structure comprises: an instruction storage unit used for storing a test command for performing a burn-in test on a memory; a test data generation unit having an input end connected to a logic control module, and an output end connected to a data write path of the memory by means of a first data channel; and a test data receiving unit having one input end connected to the logic control module, and the other input end connected to a data read path of the memory by means of a second data channel, the test data receiving unit being used for obtaining and outputting a test result of the burn-in level of the memory.
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Inventors:
HOU YONGKANG (CN)
CHEN CHUNHUI (CN)
SONG BIAO (CN)
CHEN CHUNHUI (CN)
SONG BIAO (CN)
Application Number:
PCT/CN2022/105841
Publication Date:
December 28, 2023
Filing Date:
July 14, 2022
Export Citation:
Assignee:
CHANGXIN MEMORY TECH INC (CN)
International Classes:
G11C29/12
Foreign References:
| CN113393887A | 2021-09-14 | |||
| CN106556793A | 2017-04-05 | |||
| CN107068196A | 2017-08-18 | |||
| US6415403B1 | 2002-07-02 | |||
| KR20030002161A | 2003-01-08 |
Attorney, Agent or Firm:
SHANGHAI CHENHAO INTELLECTUAL PROPERTY LAW FIRM GENERAL PARTNERSHIP (CN)
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