Title:
TEST SUBSTRATE AND MANUFACTURING METHOD THEREFOR, TEST METHOD, AND DISPLAY SUBSTRATE
Document Type and Number:
WIPO Patent Application WO/2020/140783
Kind Code:
A1
Abstract:
A test substrate, comprising: a base substrate and multiple thin film transistors provided on a first side of the base substrate. At least one of the multiple thin film transistors is a target thin film transistor to be tested. The test substrate has at least one test area, and each target thin film transistor is located in one of the at least one test area. The test substrate further comprises at least one test hole and at least one test pin which are located in the test area. The bottom of each of the at least one test hole exposes the source area, drain area, or gate of the target thin film transistor. Each of the at least one test pin is located in one of the at least one test hole; and one end of the test pin passes through the test hole to be coupled to the source area, drain area, or gate of the target thin film transistor, and the other end of the test pin is exposed to the surface of the test substrate.
Inventors:
FAN LEI (CN)
BAO ZHENG (CN)
BAO ZHENG (CN)
Application Number:
PCT/CN2019/127421
Publication Date:
July 09, 2020
Filing Date:
December 23, 2019
Export Citation:
Assignee:
BOE TECHNOLOGY GROUP CO LTD (CN)
CHENGDU BOE OPTOELECT TECH CO (CN)
CHENGDU BOE OPTOELECT TECH CO (CN)
International Classes:
H01L21/66; G02F1/1362; H01L21/77; H01L27/12; H01L27/32
Foreign References:
| CN109742037A | 2019-05-10 | |||
| CN106960805A | 2017-07-18 | |||
| CN105527769A | 2016-04-27 | |||
| CN104658970A | 2015-05-27 | |||
| CN102236179A | 2011-11-09 | |||
| CN102944959A | 2013-02-27 |
Attorney, Agent or Firm:
BEIJING ZBSD PATENT&TRADEMARK AGENT LTD. (CN)
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