Title:
THIN FILM TRANSISTOR, DISPLAY PANEL, AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR
Document Type and Number:
WIPO Patent Application WO/2013/183289
Kind Code:
A1
Abstract:
This thin film transistor has: gate electrodes (2a, 2b) positioned above a substrate (1); a gate insulating layer (3) facing the gate electrodes (2a, 2b); barrier ribs (6), which demarcate openings (6a, 6b) that include the surface of the gate insulating layer (3) therein, and which have liquid repellency higher than that of the gate insulating layer (3); semiconductor layers (8a, 8b), which face the gate electrodes (2a, 2b) with the gate insulating layer (3) therebetween, and which are respectively formed in the openings (6a, 6b) by a coating method; source electrodes (4a, 4b) and drain electrodes (5a, 5b), which are electrically connected to the semiconductor layers (8a, 8b); and intermediate layers (7a, 7b), which are composed of a material same as that of the barrier ribs (6), and which are positioned between the gate insulating layer (3) and the semiconductor layers (8a, 8b). The intermediate layers are discretely disposed above the gate insulating layer.
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Inventors:
OKUMOTO YUKO
MIYAMOTO AKIHITO
MIYAMOTO AKIHITO
Application Number:
PCT/JP2013/003528
Publication Date:
December 12, 2013
Filing Date:
June 05, 2013
Export Citation:
Assignee:
PANASONIC CORP (JP)
International Classes:
H01L29/786; H01L21/336; H01L51/05; H01L51/40; H01L51/50; H05B44/00
Domestic Patent References:
| WO2011142267A1 | 2011-11-17 |
Foreign References:
| JP2006147843A | 2006-06-08 | |||
| JP2010016280A | 2010-01-21 | |||
| JP2010232480A | 2010-10-14 |
Attorney, Agent or Firm:
NII, Hiromori (JP)
New house Extensive 守 (JP)
New house Extensive 守 (JP)
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