THREE-DIMENSIONAL FLASH MEMORY USING FRINGING EFFECT AND METHOD FOR MANUFACTURING SAME

Title:

THREE-DIMENSIONAL FLASH MEMORY USING FRINGING EFFECT AND METHOD FOR MANUFACTURING SAME

Document Type and Number:

WIPO Patent Application WO/2012/173380

Kind Code:

A2

Abstract:

A flash memory having a three-dimensional structure and using a fringing effect, and a method for manufacturing same are disclosed. A through-hole, which penetrates through a plurality of gate electrodes that are perpendicularly stacked, is formed on a substrate, and the inside of the through-hole is filled with a tunneling insulation membrane or an activated region. As a result, a charge storage layer is not formed inside the through-hole but is formed outside the through-hole. The charge storage layer is formed inside an inter-cell insulation membrane that fills a separated space between the gate electrodes. When a fringing field is applied, charge in the activated region is trapped in the charge storage field by means of the inter-cell insulation membrane.

More Like This:

JP5865214	Semiconductor devices and their manufacturing methods
JP2006196686	SEMICONDUCTOR MEMORY DEVICE, ITS MANUFACTURING METHOD, AND PORTABLE ELECTRONIC EQUIPMENT
JP2010182389	NONVOLATILE STORAGE DEVICE, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS

Inventors:

SONG YUN HEUB (KR)

Application Number:

PCT/KR2012/004639

Publication Date:

December 20, 2012

Filing Date:

June 13, 2012

Export Citation:

Click for automatic bibliography generation Help

Assignee:

IUCF HYU (KR)
SONG YUN HEUB (KR)

International Classes:

H01L27/115; H01L21/8247

Foreign References:

KR20110015339A	2011-02-15
KR20110012806A	2011-02-09
KR20110015338A	2011-02-15

Attorney, Agent or Firm:

E-SANG PATENT & TRADEMARK LAW FIRM (KR)
특허법인 이상 (KR)

Download PDF:

View/Download PDF PDF Help

Claims:

Previous Patent: PIN FOR A SEMICONDUCTOR CHIP TEST, AND SOCKET FOR A SEMICONDUCTOR CHIP TEST INCLUDING SAME

Next Patent: METHOD AND SYSTEM FOR POSITION-BASED CONSTRUCTION SITE MANAGEMENT