Title:
TRANSMISSION CIRCUIT, TRANSMISSION DEVICE, AND TRANSMISSION METHOD
Document Type and Number:
WIPO Patent Application WO/2011/148582
Kind Code:
A1
Abstract:
Disclosed is a transmission circuit which, when an envelope tracking method is employed, is capable of avoiding deterioration in linearity of output signals, minimizing distortion, and operating at high efficiency. In the transmission circuit, an offset control unit (160) sets a level of a corrected envelope signal as an offset voltage of a voltage that is greater than or equal to a level of a delayed envelope signal. The corrected envelope signal is thus greater than or equal to the level of the delayed envelope signal, allowing avoiding the power supply voltage falling below the optimal power supply voltage, as well as avoiding deterioration of linearity of the output signals in a power amplifier (130).
Inventors:
KITAMURA RYO
Application Number:
PCT/JP2011/002649
Publication Date:
December 01, 2011
Filing Date:
May 12, 2011
Export Citation:
Assignee:
PANASONIC CORP (JP)
KITAMURA RYO
KITAMURA RYO
International Classes:
H03F1/06; H03F1/02; H03F1/32; H03F3/24; H04B1/04
Domestic Patent References:
| WO2008099464A1 | 2008-08-21 |
Foreign References:
| JPH04119707A | 1992-04-21 | |||
| JP4216462B2 | 2009-01-28 | |||
| JP2009152904A | 2009-07-09 |
Attorney, Agent or Firm:
WASHIDA, KIMIHITO (JP)
Koichi Washida (JP)
Koichi Washida (JP)
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Claims: