Title:
WAVEFORM EQUALIZER CIRCUIT AND WAVEFORM EQUALIZATION METHOD
Document Type and Number:
WIPO Patent Application WO/2011/118543
Kind Code:
A1
Abstract:
Disclosed is a waveform equalizer circuit capable of easily and accurately controlling DC gain of a linear equalizer circuit according to settings. The waveform equalizer circuit is provided with a linear equalizer circuit constituted by an amplifier circuit comprising a degeneration resistance and a capacity; a DC gain control circuit for performing control by changing the value of the degeneration resistance; and a degeneration resistance control means for controlling the value of the degeneration resistance on the basis of the relationship between the value of the degeneration resistance and the level of the DC gain so that the value of the DC gain changes linearly with respect to the setting value of the control level of the DC gain; wherein the amplitude of the low frequency component of the received signal is adjusted by adjusting the setting value of the control level of the DC gain.
Inventors:
SHAO PENG (JP)
SUNAGA KAZUHISA (JP)
AMAMIYA YASUSHI (JP)
SUNAGA KAZUHISA (JP)
AMAMIYA YASUSHI (JP)
Application Number:
PCT/JP2011/056688
Publication Date:
September 29, 2011
Filing Date:
March 15, 2011
Export Citation:
Assignee:
NEC CORP (JP)
SHAO PENG (JP)
SUNAGA KAZUHISA (JP)
AMAMIYA YASUSHI (JP)
SHAO PENG (JP)
SUNAGA KAZUHISA (JP)
AMAMIYA YASUSHI (JP)
International Classes:
H03H11/04; H04B3/04; H04B3/14
Foreign References:
| JP2007174669A | 2007-07-05 | |||
| JPS62210740A | 1987-09-16 | |||
| JPS63146607A | 1988-06-18 | |||
| JP2003069355A | 2003-03-07 |
Attorney, Agent or Firm:
ASAI, TOSHIO (JP)
Toshio Asai (JP)
Toshio Asai (JP)
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Claims: