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Title:
WAVEFORM SHAPING CIRCUIT AND SEMICONDUCTOR TESTING APPARATUS HAVING THAT WAVEFORM SHAPING CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2006/035647
Kind Code:
A1
Abstract:
A semiconductor testing apparatus for surely detecting only opened edges that affect a test pattern and hence truly requires an error warning or the like. This semiconductor testing apparatus comprises real time selectors (40) and open detectors (50). The real time selectors (40) receive a plurality of waveform data outputted from a waveform memory (30) and a plurality of timing data outputted from a timing generator (20) and select and output predetermined waveform data and timing data. If an edge of the waveform data is followed by an edge of the same polarity with an interval therebetween that is shorter than a close-in limit time, then the real time selectors (40) open the following edge and output open signals. The open detectors (50) receive the waveform data, timing data and open signals outputted from the real time selectors (40) and output a fail signal if there exists an edge, which has the opposite polarity to the opened edge, within the close-in limit time preceding the foregoing opened edge.

Inventors:
OCHIAI KATSUMI (JP)
Application Number:
PCT/JP2005/017369
Publication Date:
April 06, 2006
Filing Date:
September 21, 2005
Export Citation:
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Assignee:
ADVANTEST CORP (JP)
OCHIAI KATSUMI (JP)
International Classes:
G01R31/3183; G01R31/26
Domestic Patent References:
WO1996031002A11996-10-03
WO2004008157A22004-01-22
Foreign References:
JP2000039469A2000-02-08
JPH0894711A1996-04-12
JP2002228721A2002-08-14
JPH0894722A1996-04-12
US20040051518A12004-03-18
US6291981B12001-09-18
Other References:
TAMAMA T, NARUMI N, OTSUJI T.: "New Frontiers in Testing.", KEY TECHNOLOGIES FOR 500-MHZ VLSI TEST SYSTEM "ULTIMATE"., 12 September 1988 (1988-09-12), pages 108 - 113, XP010013398
Attorney, Agent or Firm:
Watanabe, Kihei (26 Kanda Suda-cho 1-chom, Chiyoda-ku Tokyo 41, JP)
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