This disclosure relates to inductive power transfer, and in particular to a Class-E rectifier for use in an inductive power transfer circuit.

Background

Wireless power transfer has many industrial applications, and devices utilising wireless power transfer, such as wireless toothbrush chargers, wireless charging pads for mobile devices, and wirelessly charged medical devices implanted within the body, continue to grow in popularity.

Inductive power transfer (IPT) is an example of wireless power transfer (WPT). In an example inductive power transfer system, an alternating current passes through a transmitter coil. This causes the transmitter coil to produce a time-varying magnetic field. When a receiver coil is placed in the time-varying magnetic field, the magnetic field induces an alternating current in the receiver coil, which can then be used to drive a load. Thus, power is transmitted wirelessly from the transmitter coil to the receiver coil through the time-varying magnetic field.

Strongly coupled inductive links tend to operate in the tens to hundreds of KHz region. In contrast, weakly coupled inductive links tend to operate in the low MHz region in order to increase their link efficiency (njink). The optimal link efficiency (nimk.opt) of an inductive link can be described by:

where parameter k is the magnetic coupling between the coils forming the link and Qrx and Qtx are the unloaded quality factors of the receiving (L _re ) and transmitting (/_&) coils respectively. The unloaded quality factor of a coil can be defined as the ratio of the reactance of the coil to the equivalent series resistance of the coil at a particular frequency. In inductive links with air core coils the coupling factor can vary from approximately 1 % to approximately 10%. Such coupling factor values are relatively low when compared to inductive links that utilise ferrite in their coils. Hence, weakly coupled inductive links tend to operate in the low MHz region in order to increase their optimal link efficiency (n,iink,o _P t) by increasing the unloaded quality factors of the coils forming the link compensating for the low coupling factor.

The optimal link efficiency of a particular inductive link geometry occurs when the receiving coil is tuned at the frequency of the generated magnetic field, and the ratio of the ac load resistance (R _ac ) to the reactance of the tuning capacitor (Crx) satisfies a certain value (a _op t). The a _op t value is defined in the following two expressions and it depends upon the coupling factor between the coils forming the inductive link, the unloaded quality factors of the two coils, and the tuning method of Ux, parallel (Fig. 1 a) or series (Fig. 1 b).

When a rectifier is added to an inductive link, for example when a rectifier is added to the receiver side circuit of any of Figs 1 a-b, its input resistance will be the ac load. Accordingly, the rectifier should be chosen according to optimal link efficiency requirements. Furthermore, the rectifier topology should be chosen such that it is efficient at the frequency of operation; it is compatible with the output type of the tuned receiving coil, whether that be voltage output for parallel tuned receiving coil (Fig. 1 a) or current output for series tuned coil (Fig. 1 b); and such that its input reactance is absorbed by Crx such that the tuning of L _n is unaffected. Class-E rectifiers are considered good possible candidates for integration in multi- MHz applications due to their efficient soft-switching capability and the consequent low electromagnetic interference (EMI) operation this allows. Summary

An invention is set out in the independent claims. Optional features are set out in the dependent claims.

Disclosed herein is a rectifier circuit for receiving an AC signal from a receiver coil in an inductive power transfer system is provided. The circuit comprises a Class-E rectifier, and is configured to operate at an operating frequency. The circuit comprises a resonant network having a resonant frequency, wherein the ratio of the resonant frequency to the operating frequency is within the range of 1 .75 to 3.

According to a first aspect, a rectifier circuit for receiving an AC signal from a receiver coil in an inductive power transfer system is provided. The circuit comprises a Class-E rectifier and an AC signal supplier configured to supply an AC signal to the rectifier circuit. The circuit is configured to operate at an operating frequency. The circuit comprises a resonant network having a resonant frequency. The resonant network is an LC network comprising an inductor and a capacitor, and the ratio of the resonant frequency to the operating frequency is within the range of 1 .75 to 3. The AC signal supplier may be separate and discrete from the resonant network, and in turn the resonant network may be separate and discrete from the AC signal supplier. In particular, the inductor and the capacitor of the resonant network may be separate and discrete from the AC signal supplier. In embodiments where the AC signal supplier is a receiver coil arranged to receive an AC signal and introduce and/or supply the AC signal to the rectifier circuit, the resonant network and its constituent components may be separate and discrete from the receiver coil. In particular, the inductor of the resonant network may be external to the AC signal supplier, and in particular may be external to a receiver coil. Hence, the inductor may be comprised outside of the receiver coil, and be arranged in the rectifier circuit to provide an inductance in addition to any inherent inductance of the AC signal supplier. Optionally, the inductor of the resonant network may be coupled to the AC signal supplier. The inductor may be directly coupled to the Ac signal supplier.

Optionally, the inductor of the resonant network may be arranged in series with the AC signal supplier. Optionally, the circuit comprises the receiver coil. In other words, the AC signal supplier comprises the receiver coil.

Optionally, the receiver coil is an air core coil.

Optionally, the operating frequency is determined by the AC signal from a receiver coil. Optionally, the rectifier circuit is coupled to a Class-D inverter, and the operating frequency is determined by the output frequency of the Class-D inverter.

Optionally, the rectifier circuit is coupled to a Class-E inverter, and the operating frequency is determined by the output frequency of the Class-E inverter.

Optionally, the rectifier circuit is coupled to a Class-EF inverter, and the operating frequency is determined by the output frequency of the Class-EF inverter.

In other words, the AC signal supplier may be a receiver coil and/or an inverter. The inverter may be a Class-D inverter, a Class-E inverter, a Class-EF inverter, or any inverter disclosed herein.

Optionally, the inverter is arranged to drive a load resistance, and comprises a switching device arranged between a power source and ground and arranged to switch at a switching frequency. A resonant network is arranged in parallel with the switching device between the power source and ground, the resonant network having a resonant frequency which is a non-integer multiple of the switching frequency, such that, in operation, a substantially constant current passes through the load resistance.

Optionally, the operating frequency is determined by the output frequency of a resonant tank circuit comprising an inductor and a capacitor. Optionally, the ratio of the resonant frequency to the operating frequency is within the range 1 .75 to 2, optionally within the range 1 .8 to 2, and optionally in the range 1 .8 to 1 .9.

Optionally, the rectifier circuit further comprises a diode, and optionally wherein a parallel capacitor is placed across the diode.

Optionally, the AC signal is an input voltage; the capacitor of the resonant network is coupled to the input voltage and has a capacitance C _s ; and the parallel capacitor has a capacitance C _P , the ratio of C _P to Cs being above zero. Advantageously, such a hybrid class-E rectifier can emulate any input ac resistance for any given dc resistance (Rdc).

Optionally, the rectifier is a non-synchronous rectifier.

Optionally, the ratio of the resonant frequency to the operating frequency is within the range 2 to 3.

Optionally, the rectifier circuit further comprises a transistor. Optionally, the rectifier is a synchronous rectifier.

According to another aspect, a combined inverter-rectifier circuit comprising a rectifier circuit coupled with an inverter circuit is provided. The rectifier circuit is as described above and herein, and the inverter is suitable Class 'EF' operation. The inverter is arranged to drive a load resistance, and the inverter comprises a switching device arranged between a power source and ground, the switching device arranged to switch at a switching frequency. The inverter also comprises a resonant network arranged in parallel with the switching device between the power source and ground, the resonant network having a resonant frequency which is a non-integer multiple of the switching frequency, such that, in operation, a substantially constant current passes through the load resistance.

Disclosed herein is a combined inverter-rectifier circuit comprising a rectifier circuit coupled with an inverter circuit is provided. The rectifier circuit is as described above and herein, and the inverter is suitable Class 'EF' operation. The inverter is arranged to drive a load resistance, and the inverter comprises a switching device arranged between a power source and ground, the switching device arranged to switch at a switching frequency. The inverter also comprises a resonant network arranged in parallel with the switching device between the power source and ground, the resonant network having a resonant frequency which is a non-integer multiple of the switching frequency, such that, in operation, a substantially constant current passes through the load resistance.

According to another aspect, a Class-E inverter circuit for driving a transmitter coil in an inductive power transfer system is provided. The inverter is arranged to drive a load resistance and comprises a switching device arranged to switch at a switching frequency, and a resonant network arranged in parallel with the switching device. The circuit is arranged such that, at the moment the switching device is switched on, a voltage across the switching device is zero or substantially zero and a time derivative of the voltage is negative; and at the moment the switching device is switched off, a voltage across the switching device is zero or substantially zero. According to another aspect, a method of switching a switching device in a Class-E inverter circuit is provided. The inverter is arranged to drive a load resistance, and comprises a switching device arranged to switch at a switching frequency, and a resonant network arranged in parallel with the switching device. The method comprises switching the switching device on when a voltage across the switching device is substantially zero and a time derivative of the voltage is negative; and switching the device off when a voltage across the switching device is substantially zero.

Optionally, the load resistance comprises the reflected resistance of at least one receiver coil. Optionally, the load resistance comprises the reflected resistance from a receiving resonant tank circuit.

Optionally, the inverter is coupled to the rectifier of any of claims 1 to 16. Optionally, the switching device is a transistor. Optionally, the inverter circuit comprises a capacitor arranged in parallel with the switching device.

Optionally, the resonant network comprises an inductor and a capacitor arranged in series with each other.

Figures

Specific embodiments are now described with reference to the drawings, in which: Figure 1 a depicts a circuit arrangement comprising a parallel tuned receiving coil. Figure 1 b depicts a circuit arrangement comprising a series tuned receiving coil. Figure 2a depicts a circuit arrangement comprising a Class-E zero dv/dt rectifier. The rectifier depicted is a hybrid rectifier.

Figure 2b depicts a circuit arrangement comprising a Class-E zero dv/dt rectifier. The rectifier depicted is a current-driven rectifier.

Figure 2c depicts a circuit arrangement comprising a Class-E zero dv/dt rectifier. The arrangement shown is a voltage driven rectifier with a series capacitor.

Figure 2d depicts a circuit arrangement comprising a Class-E zero dv/dt rectifier. The arrangement shown is a voltage driven rectifier with a series inductor.

Figure 3a depicts the variation of design variables for a current driven rectifier as shown in Figure 2b;

Figure 3b depicts the variation of design variables for a voltage driven rectifier as shown in Figure 2c;

Figure 4a depicts variation of the loaded Q for a voltage driven rectifier with a series inductor.

Figure 4b depicts variation of the loaded Q for a hybrid rectifier, current driven rectifier and voltage driven rectifier with a series capacitor.

Figure 5a shows the performance of different rectifier designs at a constant dc load resistance.

Figure 5b shows a series input resistance and reactance of a rectifier in accordance with the present disclosure (design #4) at variable dc load.

Figure 5c shows a series input resistance and reactance of another rectifier according to the present disclosure (design #5) at variable dc load. Figure 5d shows a series input resistance and reactance of a rectifier (design #2) at variable dc load.

Figure 6a shows experimental data, and in particular shows the experimental data shown in figure 5b, mapped onto contours of link efficiency, reflected resistance to the transmitting coil, and reflected reactance to the transmitting coil. From 80% to 95% the contours appear in steps of 1 % and from 95% to 99% in steps of 0.5%. Figure 6b shows experimental data, and in particular shows the experimental data shown in figure 5c, mapped onto contours of link efficiency, reflected resistance to the transmitting coil, and reflected reactance to the transmitting coil.. From 0.1 to 1 the contours appear in steps of 0.1 and the in steps of 1.

Figure 6c shows experimental data, and in particular shows the experimental data shown in figure 5d mapped onto contours of link efficiency, reflected resistance to the transmitting coil, and reflected reactance to the transmitting coil. From 0 to 0.1 the contours appear in steps of 0.02, then from 0.1 to 0.2 in steps of 0.1 , and then in step of 0.2.

Figure 7 depicts a circuit arrangement for a Class-EF inverter which may be coupled to rectifier arrangements of the present disclosure.

Figure 8a depicts a hybrid synchronous Class-E rectifier in accordance with the present disclosure.

Figure 8b depicts a current driven synchronous Class-E rectifier in accordance with the present disclosure.

Figure 8c depicts a voltage driven series-C synchronous Class-E rectifier.

Figure 8d depicts a voltage driven series-L synchronous Class-E rectifier in accordance with the present disclosure.

Figure 9 depicts a Class-E inverter which may be coupled to rectifier arrangements of the present disclosure.

Figure 10 depicts a Class-D inverter which may be coupled to rectifier arrangements of the present disclosure. Overview

It has previously been thought that, in a Class-E Zero dv/dt rectifier, it was necessary for the rectifier to exhibit a resistive input impedance. It was thought that a resistive input impedance was required due to a requirement by further inductor-capacitor networks added in the circuit to compress the load seen by the inverter as the output dc load varies.

However, existing arrangements struggle with two problems. First, the Class-E rectifier's input reactance varies as the dc load of the system changes. Second, it has proved difficult to regulate the output voltage of prior systems.

As will be discussed in further detail below, existing approaches to solve these problems necessarily involve energy storage components and/or additional external circuitry. However, these additional components are volume consuming, take up PCB real-estate, and unduly increase the physical size and weight of the system. These components also increase the cost of the system. It will be appreciated that this is not ideal in a commercial WPT application. The variable Ar can be defined as the ratio of the resonance frequency of the LC network (ω _Γ ) of the Class-E rectifier to the operating frequency (ω). A Class-E rectifier circuit with an Ar larger than 1 .5 has never been considered, let alone designed before, because of the prevailing assumption in the art that the Class-E rectifier should be designed to present a resistive input impedance. With this prevailing assumption in mind, the vast majority of Class-E rectifiers in the prior art have an Ar that tends to 0. Again with this prevailing assumption in mind, in some specific arrangements the Ar value may either equal to 1 , or be as close to 1 as possible. As will be discussed in greater detail below, the provision of a Class-E Zero dv/dt rectifier with an Ar between 1 .75-3 has been found to address these problems. In particular, a Class-E Zero dv/dt non-synchronous rectifier topology designed with an Ar in the range of 1 .75-2, and a Class-E Zero dv/dt synchronous rectifier topology designed with an Ar in the range of 2-3, exhibit low deviation in input reactance by the rectifier as the load on the system changes, and inherent output voltage regulation with variation of the dc load (Rdc). Detailed Description

Fig.1 a and Fig.1 b show inductive link circuit configurations, each having a simple transmitter circuit 120 and a simple receiver circuit 130. Each of the transmitter and receiver circuits has a coil, and the magnetic coupling of the coils of the transmitter and receiver circuits can be represented by k. A current source 102 introduces a current l _ac into the transmit side circuit. The transmit coil 104 has an inductance Ltx.

The receiver side circuit comprises a receiver coil 106 having an inductance Ux. In Fig. 1 a, a capacitor 108a having a capacitance Crx is arranged in parallel with a load resistance 1 10a having a resistance R _ac , par. In Fig. 1 b, a capacitor 108b having a capacitance Crx is arranged in series with a load resistance 1 10b having a resistance

Rac, ser. Throughout Figs. 2a-d, like numerals refer to like components. Figs. 2a-d show hybrid and conventional Class-E half-wave zero dv/dt rectifiers. Fig 2a shows a hybrid rectifier (HVDR). Fig. 2b shows a current-driven rectifier (CDR). Fig. 2c shows a voltage driven rectifier with a series capacitor (series-C VDR). Fig. 2d shows a voltage driven rectifier with a series inductor (series-L VDR). The skilled person will appreciate the arrangement of the depicted components from the figures.

The topology shown in figure 2a is a new topology: a hybrid Class-E rectifier. The hybrid Class-E rectifier combines the properties of the voltage driven Class-E rectifier with a series capacitor, and the current driven Class-E rectifier. However, the parasitic effects of the diode negatively affect the properties of the circuit. This beneficial combination of properties is achieved, and the parasitic capacitance of the diode is mitigated, by adding an external capacitor C _P across the diode. Capacitor C _P to absorb the parasitic capacitance of the diode, as in the current driven rectifier, while having a series capacitance (Cs) between the input voltage source and the rest of the circuit, as in the voltage driven Class-E rectifier with a series capacitor.

In Fig. 2a, the depicted rectifier is powered by an ac input voltage 202a. The input voltage 202a supplies an ac signal to the rectifier. In IPT implementations, the input voltage could be supplied by a receiver coil, which is arranged to receive a signal from a transmitter coil. In operation as part of an IPT system, a receiver coil receives power from a transmitter coil and thus acts as a source of ac voltage for the rectifier circuit. The arrangement shown in Fig. 2a also comprises an inductor 210a having an inductance L, and a dc load 214a having a resistance Rdc. Vdc represents the dc output voltage across the dc load 214a. A filter capacitor 212a having a capacitance Cf is placed across the output resistance 214a. In the HVDR of Fig. 2a, a first capacitor 206a is coupled to the input voltage source 202a, and a second capacitor 204a is placed across a diode 208a. The first capacitor has a capacitance Cs. The second capacitor has a capacitance C _P . Thus, the capacitance C of the system is split into Cs and C _P . Since an external capacitor is arranged across the diode 208a, the capacitance C _P n of the diode 208a can be physically absorbed by C _P .

The hybrid class-E rectifier can emulate any input ac resistance for any given dc resistance (Rdc) based on a variable B. Variable B is defined as the ratio of C _P to Cs. To achieve the emulation, variable B should be greater than 0 and can go up to infinity. This property can be achieved with either a synchronous or non-synchronous rectifier.

The arrangement shown in Fig. 2b is a current-driven rectifier. The rectifier is structurally similar to the hybrid rectifier depicted in Fig. 2a, however capacitor 204a is not present, and the input voltage is replaced by an input current 202b.

The arrangement shown in Fig. 2c is a voltage driven rectifier with a series capacitor 206c having a capacitance C. The rectifier is structurally similar to the hybrid rectifier depicted in Fig. 2a.

The arrangement shown in Fig. 2d is a voltage driven rectifier with a series inductor 21 Od. The inductor 21 Od is coupled to an input voltage 202d. The inductor 21 Od is also coupled to a diode 208d. A capacitor 216d is arranged across the diode 208d. The arrangement shown, outputs a dc voltage Vdc which is output across an output resistance 214d. A filter capacitor 212d having a capacitance Cf is arranged across the output resistance 214d.

As Ar is increased above 2, the current in the semiconductor must be able to flow in both directions. This is because, as the resonant frequency of the L-C network in the rectifiers (or L-C _S -C _P network for the hybrid rectifier) is greater than the operating frequency in these arrangements, the magnitude of the current harmonics (current waveforms of greater frequency than the operating frequency) can be greater than in the case where the resonant frequency would have been smaller than two times the operating frequency (i.e. A _r <2). As the magnitude of the current harmonics is now higher, the current through the transistor has oscillations that would result in a bidirectional current. These oscillations have a frequency approximately 1 .5 times the operating frequency. Hence, in embodiments which operate with an Ar greater than 2, a transistor may replace the diode 208a-d. Typically, when a diode is used in the circuit, the rectifier may operate as a non-synchronous rectifier, and an Ar in the range of 1.75 to 2 may be used. When a transistor replaces the diode, the rectifier may operate as a non- synchronous rectifier, and an Ar in the range of 2 to 3 may be used. However, it will be appreciated that the substitution of the diode for a transistor in the Ar range of 1 .75 to 2 is optional.

Figures 8a to 8d show a hybrid synchronous Class-E rectifier, a current driven synchronous Class-E, a voltage driven series-C synchronous Class-E rectifier and a voltage driven series-L synchronous Class-E rectifier respectively. As will be appreciated, these circuit arrangements are similar to those shown in figures 2a-d, with a diode 208 being replaced with a transistor 808. These circuits can be used across the full range of Ar, from 1 .75 to 3. In figures 2a-d and figures 8a-d, like reference numerals are used for structurally and/or functionally similar circuit components.

As the skilled person will appreciate, conduction losses in a transistor are generally lower than in a diode when the semiconductors of these components conduct the same current. This is due to the forward voltage drop across the diode. A transistor does not experience this type of conduction loss, since its current conducting capability is controlled by an external signal. The external signal may be provided, for example, by a gate drive circuit. The gate drive circuit typically comprises further transistors which are capable of providing the required amount of charge to the gate capacitance of the transistor of the power circuit. The transistors within the gate drive circuit are controlled by a digital, i.e. small, signal, which could be provided by, for example, a microcontroller. Gate drive circuits are commercially available circuits and come in different packages, with different charging capabilities (e.g. speed for the delivery of a specific amount of electric charge).

While operating in the MHz region, the external signal could consume higher power than that required to forward bias the diode. However, modern transistor technologies achieve MHz switching with insignificant power requirement for the control signal.

Furthermore, since a transistor can be controlled by an external signal, an advantage of synchronous rectification is the ability of the circuit to regulate either the output voltage or the output current by varying the parameters of the external control signals. In the case of synchronous Class-E rectifiers, such parameters include the time of conduction of the transistor within one operating frequency (i.e. the duty cycle) and the phase between the control signal and the input source of the rectifier (i.e. the phase angle). Another advantage of having A _r greater than 2 is that the variation in duty cycle with output load variation becomes smaller than the variation in duty cycle when Ar is between 1 .75 and 2.

There are two operating modes for synchronous rectification when Ar is greater than 2, that are differentiated based on the phase angle between the control signal of the transistor and the input ac source. In the first, the phase angle is variable and changes such that zero voltage and zero derivative switching will be achieved during the turning off of the transistor. In the case of the non-synchronous rectifier, because the diode does not conduct current when the voltage across it is negative, the phase angle varies inherently with output load and zero derivative switching always occurs independent of the load. In the second and preferred operating mode, the rectifier is a synchronous rectifier, wherein the phase angle is kept constant at a value where at 100% load the rectifier will achieve zero voltage and zero voltage derivative switching. By keeping the phase angle constant as the output load changes, zero voltage switching can be maintained. Zero derivative switching may be lost as the dc load decreases below 100%, however because the voltage at the point of switching is still zero, switching losses are still insignificant compared to the conduction losses. Being able to keep the phase angle constant in synchronous rectifier circuits is beneficial since external circuitry that would adapt the phase angle to the correct value based on the load is no longer required.

The properties of inherent voltage regulation and low input reactance deviation are still maintained as A _r increases above 2, and in particular are maintained across the range of 1 .75 < A _r < 3. In fact, the error in inherent voltage regulation decreases below 5% as Ar increases beyond 2, for both varying and constant phase angle operation.

Each of the arrangements shown in Figs. 2a-d is designed to operate at an operating frequency. In the case of an IPT arrangement, the operating frequency may be determined by the frequency of the magnetic field generated at the transmitting coil. The frequency of the generated magnetic field is determined by the inverter driving the transmitting coil. In the case of any inverter, the frequency of the generated magnetic field is equal to the switching frequency of the transistor in the transmitting circuit.

As will be appreciated, each of the arrangements shown in Figs. 2a-d, have a resonant network. Resonant network include LC networks. In Figs. 2a-d, the resonant network is comprised of a capacitance C, and an inductance L. In Fig. 2a, the capacitance C is provided by capacitors 206a and 204a. The inductance is provided by inductor 210a. These components can be chosen to give different L and C in order to tune the resonant frequency ω _τ of the network.

The resonant frequency is defined as the frequency at which L and C will have the same reactances. The reactance of L equals to ωΙ_ and the reactance of C equals to 1/((JUC). The physical meaning of resonance is the phenomenon where all the energy stored in the magnetic field of the inductor is transformed into electric energy stored as electric field in the capacitor. In embodiments of the present disclosure, the circuit is designed such that the ratio of the resonant frequency of the Class-E rectifier to the operating frequency of the circuit is preferably in the range 1 .75 to 3.

In IPT applications, the input of the rectifier circuit, 202a-d, may be a receiving coil. The receiving coil may be a ferrite core coil, or an air core coil. Air core coils may be described as any inductor which does not rely on a ferromagnetic material to operate. Air core coils in an IPT system can be described as 'weakly coupled', because the achievable magnetic coupling between coils is relatively low when compared to inductive links that utilise e.g. ferrite in their coils. The term air core coil may describe inductors having a conducting coil comprised, for example, of wire, and which has air inside the turns of wire. Inductive links with air core coils are more robust to coil misalignments and can operate at greater gaps than links with, for example, ferrite core coils. Furthermore, air core coils are cheap and light as they do not use ferrite. Air core coils are also more reliable as there are no effects of ferrite degradation. However, it will be appreciated that the presently disclosed arrangement is beneficial for any type of coil.

Class-E zero dv/dt rectifiers, as shown in Figs. 2a-d, use a capacitor having a capacitance C, or a capacitive network of total capacitance C, to achieve zero rate of change of the voltage across a diode when it is reverse biased. An inductor having an inductance L is used for the circulation of the dc load current when the diode is forward biased. It is possible to describe the operation of Class-E rectifiers according to a variable Ar, defined as the ratio of the resonance frequency of the LC network (our) to the operating frequency (ω). The operating frequency is the frequency of the input ac source. Where ω _Γ equals to ω, Ar is equal to unity, and the rectifier is therefore operating at resonance.

In the Class-E rectifiers of Fig. 2a-d, the inductor, L, functions as a filter inductor and, in operation, has a large harmonic distortion in the current through it (ii_). When the diode is forward biased, one end of the inductor can be clamped to ground, causing a constant rate of discharge of Cf through L. When the diode is reverse biased, ii_ has a sinusoidal component superimposed to the output dc current. The magnitude of the ac component of ii_ increases with A _r . When A _r approaches zero in operation above resonance, the current through L can be assumed to be dc.

As is known to the skilled person, the source of a network is the part of the network that provides or transmits power, and the load is the part of the network which consumes power. In the arrangements shown in Figs 2a-d, the input sinusoidal source of the rectifiers may be the output of a resonant tank. The resonant tank can be either the receiving end of an IPT system (e.g. Lrx— Crx of Fig. 1 ) or it can be part of the output network of an inverter. In the latter case the rectifier will be directly connected to the inverter forming a resonant dc to dc converter. Prior Class-E rectifiers have been designed to exhibit a resistive input impedance due to a requirement by further inductor-capacitor networks added in the circuit to compress the load seen by the inverter as the output dc load varies. A resistive input impedance was thought to be necessary because designing a circuit with a resistive input impedance means that, for a perfectly tuned coil, there will be no exchange of reactive power across the link. Any exchange of reactive power will result in higher currents in the coils for the same real power delivered to the load and therefore more losses.

However, in arrangements of the present disclosure it has been appreciated that the input impedance does not have to be purely resistive. To ensure high efficiency, the presence of that extra reactance can be compensated for, and the circuit can be designed such that the extra reactance does not deviate at variable loads and its deviation does not detune the receiving coil of the IPT or the resonant tank in a resonant converter.

A first problem in the operation of known circuits is the variation of the input impedance of the Class-E rectifier as the output dc resistance changes, e.g. due to a change in the state of charge of a battery powered directly by the rectifier. The resistive input impedance property of a Class-E rectifier is valid for a specific output dc load (Rdc). As the output dc load changes the input impedance of the rectifier may also be changed such that it is no longer resistive. This affects other parts of the system, for example the inverter or the inductive link and the transmitting end in the case of an IPT system. In IPT and resonant power converter applications, the incorporated resonant tanks need to remain unaffected. In the case of an inductive link, this is particularly important because the resonant tank at the receiving end must always be in resonance at the frequency of operation such that optimal link efficiency conditions can be met. In the case of a resonant converter, the resonant tank must not be detuned, otherwise optimal soft switching conditions for the utilised inverter are lost, causing system efficiency to be negatively affected.

One method which attempts to solve the problem of input reactance variation with dc load is the addition of a dc/dc converter after the rectifier. The external dc/dc converter provides a constant load for the rectifier, and hence keeps its input impedance, and thus its input reactance, constant at all times. However, this method is unsatisfactory as it requires the addition of an extra power conversion block in the system. The efficiency of the added dc/dc converter will reduce the efficiency of the complete system while increasing the cost of the system.

Another method which attempts to solve the problem of input reactance variation with dc load is to modify the inverter such that the variation of the reactance of the rectifier does not affect the soft switching operation of the inverter. However, this method is also unsatisfactory as it requires the addition of external circuitry that not only increases both the cost and the size of the inverter, but also reduces the efficiency of the system.

A second problem in the operation of known circuits is the regulation of the output voltage of the system.

In general, a rectifier circuit will provide power to a specific load, such as a battery or a drive rotating the motor of an electric vehicle. It is common for the rectifier to have a requirement to regulate any of the voltage, current or power that is supplied to the load. Because the diode in the rectifier circuit cannot be controlled by an external signal, the controlled signal is applied to the transistor. In the pulse-width-modulated (PWM) dc/dc converters (e.g. buck, boost, forward converter) any type of regulation at the output is achieved by varying the width of the pulse that defines the conduction time of the transistor in the circuit, hence the name given to these converters.

However, in resonant converters utilising soft-switching topologies, such as Class-E inverters/rectifiers, pulse width modulation is not common because the behaviour of the circuit with duty cycle is difficult to be predicted. Simpler methods of control are applied that essentially stop and initiate the transmission of power from one end of the system to the other based on the output voltage value. This method of control, while simple, requires energy storage components at the output that are able to provide power at the output when no power is transferred to the rectifier. Energy storage components are volume consuming, increasing therefore the physical size and weight of the system. For a successful Class-E rectifier integration in an IPT system, the input resistance of the topology should be set to an optimal value based on the configuration of the inductive link. It is mathematically convenient to represent the input impedance of the voltage driven Class-E rectifiers as the parallel connection of a reactive component, Χίη,ρ, and the input resistance, Rin, _P . On the other hand, in the current driven topology it is more convenient to present the input impedance by a series combination between Xi _n;s and Rin _;s . When Class-E rectifiers are designed to provide optimal link efficiency conditions, designers can select the duty cycle, d _r , at full load and variable A _r :

Ar = - (4)

The choice of 50% duty cycle at full load tends to provide maximum power output capability (cpdc) in Class-E rectifiers. In the case of the HVDR (Fig. 2a) another degree of freedom is introduced in the selection of variable B defined as:

(5)

where the sum of the two capacitances is:

C = C _S + C _P (6) The passive components in the circuit are then evaluated such that the specified conditions are met.

The duty cycle depends on the loaded quality factor (Qr) of the rectifier, defined as: Q _r = ^f (7) where Rdc is the rectifier's dc load and X is the reactance of the series component in the voltage driven topologies (L or C) or in the current driven topology, X is the reactance of capacitor C. The relationship between the dc resistance with the input resistance in the voltage driven rectifiers (assuming 100% efficiency) is given by:

Roc = 2M _v ² R _iniP = 2M _v ² R _aCiPar (8) where Mv is the ratio of output voltage to the peak of the ac input voltage (ac to dc voltage gain). In the current driven topology, Rdc is given by:

R _dc = =≤ £≤r (9) where Mi is the ratio of output current to the peak of the ac input current (ac to dc current gain). In order to directly relate the input ac resistance to the required X value, (8) and (9) are substituted into (7) and the variables are rearranged such that an expression is formed relating the ratio of the ac resistance to the required X value. This ratio will be called input loaded quality factor, Qin, and is given by the following expressions:

for the voltage driven topologies and:

Q _IN = 2M _j ² Q _R = ^ (1 1 )

for the current driven topology. Using the definition of variable A _r , the relationship between the reactances forming the LC network is given by: Ar ² = T _L ( ^{1 2} )

In the case of the HVDR, Cs and C _P are evaluated from (5), (6) and (12). Finally, the ratio of input reactance to X is given by:

in = ^ (13)

In the mathematical analysis of each rectifier, the diode and passive components were assumed ideal and lossless. The design variables in (7) - (1 1 ) and (13), for the Class-E topologies are presented in Fig. 3a-c and Fig. 4 as functions of A _r for duty cycle values from 50% to 10%, in steps of 10%. In Fig. 5 the design variables are illustrated as functions of Ar for several values of B at 50% duty cycle for the HVDR. The loaded quality factor (Q _r ) is independent of variable B and is therefore the same for the HVDR (Fig. 2a) and the series-C VDR (Fig. 2c). Also, Qr in the CDR (Fig. 2b) is the same as in HVDR and the series-C VDR since CDR forms the Norton equivalent circuit of the series-C VDR.

The CDR (Fig. 2b) is the most commonly implemented topology of the conventional half-wave Class-E rectifiers. However, a crucial property of the topology has been missed in the prior art, because as can be seen for Nin in Fig. 3a, an Ar between 1 .75 to 2 has the advantage of keeping the input reactance of the topology, Xin _;s , less than 5% from its initial value as the duty cycle decreases below 50% as a result of increasing Rdc. Hence, the CDR will not significantly detune the receiving coil because it will not introduce a large residual reactance compared to the reactance of Lrx, as Rdc increases. In the same Ar range (1 .75 to 2) unlike Xin _;s the input resistance (Ri _n;s ) of the topology will change with duty cycle. From the definition of Qin and by considering the behavior of duty cycle with Rdc, the input resistance of the topology decreases as Rdc increases. This behavior of Ri _n;s provides an inherent output voltage regulation assuming a constant input current. The inherent output voltage regulation can be observed by multiplying Mi and Qr. From the definitions of the two variables, their product gives a direct relationship between the input current and the output voltage: Vdc /(Xc . iin). By evaluating the product of the curves in Fig. 3a with the curves in Fig. 3d it can be observed that there is an insignificant deviation from the initial value of this product as the duty cycle decreases below 50%. In fact the inherent voltage regulation actually occurs over a range of Ar from 1 .6 to 2.

In resonant operation, a monotonic behavior of the input resistance of the topology can be observed in Qin of Fig. 3a. Rin _;s increases with Rdc. Inherent output voltage regulation can exist in resonant operation by keeping the induced emf in the receiving coil constant. However, the error in output voltage regulation is more difficult to find in this case without considering the value of the external capacitor added for the tuning of the receiving coil and the system is not as well regulated as in operation at an A _r between 1 .6 and 2.

Finally, when the topology is designed at an Ar that tends to zero the resultant inductance value (L) is large. This can be deduced from Qin of Fig. 3a and (12). A high inductance results in an inductor current (il_) with a small ac component. This small ac component eases the implementation of the output filter capacitor (Cf).

Turning to the series-L VDR (Fig. 2d), the series-L VDR will generally introduce implementation challenges because the required inductance L will need to be in the μΗ range for most practical inductive links. Using the definition of Qin in the series-L VDR, it can be shown that the ratio of L to Lrx will be greater than unity when Ar is greater than 0:5. Realising these values of inductance requires a magnetic core which will be prohibitively lossy at MHz frequencies.

Turning to Voltage Driven Class-E Rectifier with Series Capacitor (series-C VDR), this topology (Fig. 2c) can be thought as the voltage driven equivalent of the CDR (Fig. 2b) and therefore, it exhibits the same input impedance behavior with Ar. As Ar tends to zero a large L results from the design variables which eases the implementation of Cf . In resonant operation (Ar is one), a monotonic behavior of the input resistance of the topology (Rin _;P ) can be observed in Qin of Fig. 4b (centre). Ri _n;P decreases as Rdc increases and hence, as observed in the CDR (Fig. 2b), the equivalent series resistance seen by LR _x increases with Rdc resulting in inherent output voltage regulation when the induced emf is constant.

From Nin in Fig. 3b, it can be shown that the property of low input reactance (Xin;p) deviation with increasing Rdc occurs over the same Ar range as the CDR (from 1 .75 to 2). Furthermore, the inherent output voltage regulation at the aforementioned Ar range can be observed in Mv of Fig. 3b. In the Ar range from 1 .75 to 2, Mv changes insignificantly from its initial value as Rdc increases. Hence, by keeping constant the voltage across the input terminals of the rectifier the output voltage will be regulated. In an IPT scenario the input voltage of the rectifier is the voltage across the tuning capacitor and will be kept constant by keeping constant the current in the receiving coil (as in the CDR). Rin;p is an order of magnitude greater than Xin;p to satisfy the optimal link efficiency conditions, therefore the magnitude of the voltage at the input terminals of the rectifier is primarily dependent on Xin;p. As Xin;p remains within 5% of its initial value at this Ar range, at a constant La the voltage across the input terminals of the rectifier remains constant.

In contrast to the other rectifier topologies, the operation of the series-C VDR is highly dependent on the output power level because the non-constant diode junction capacitance (Cpn) is not absorbed into a large fixed capacitor. Therefore, the HVDR (Fig. 2a) can be seen as an improvement to the series-C VDR because Cpn can be absorbed into Cp. Hence, the HVDR is more robust to changes in output voltage than the series-C VDR and introduces an additional degree of design freedom in the selection of variable B, which allows the provision of optimal load for a desirable Ar.

Finally, turning to the Hybrid Class-E Rectifier (HVDR), the behaviour of Mv, Qin and Xin variables over Ar and dr in both the HVDR (Fig. 2a) and the series- C VDR (Fig. 2c) is the same and hence, these two topologies share the advantageous properties discussed in the previous section. However, an additional important property of the HVDR (Fig. 2a) can be observed by considering the ac to dc gain (Mv). In this topology Mv depends on two variables, Ar and B. The series-C VDR does not have this property because it does not split C into two components. By selecting the appropriate Ar and B combination, the topology can be used to match the optimal ac load of an inductive link to any given value of Rdc to be powered by the IPT system. Furthermore, different HVDR topologies can present the same ac load while having the same Rdc but with different values of the other passive components. It should be noted that for Ar greater than 1 :7, the input capacitance of the HVDR can become greater than Crx. For the purposes of better illustrating the present concepts and findings, the results of an examination of five different rectifier designs will now be discussed and presented. • Design #1 : HVDR operating at an Ar smaller than one providing a low ac current ripple through the output filter capacitor.

• Design #2: HVDR operating at resonance (Ar =1 ) and exhibiting a monotonic behavior in its input resistance with varying Rdc.

· Design #3: HVDR operating at the maximum power output capability (cPdc ) point of Fig. 6 (Ar =1 .52).

• Design #4: HVDR operating at an Ar equal to 1 .75, exhibiting a low deviation input reactance and a monotonic behaviour in input resistance with varying Rdc.

• Design #5: CDR with the same input impedance properties as Design #4 (Ar =1 .8).

The four HVDR designs were implemented with a different combination of Ar and B to investigate which combination of LC network components will deliver the best efficiency and the required input resistance for the same Rdc. All the HVDR designs had the same Mv, except Design #4, since B has to be evaluated to yield an input capacitance smaller than the tuning capacitance of Lrx. Ar in the CDR (Design #5) was selected to also result in a circuit with Rdc equal to the value for the other rectifiers.

For each design, the inductor (L) was implemented first. Based on its measured value the other passive components were chosen such that the initial selection of Ar and B, or just Ar for the CDR, was satisfied. All inductors were implemented with Micrometals iron powder cores for RF applications. Specifically, in Design #1 a T106-3 core was used and in Designs #2 to #5 T106-2 cores were used. All capacitors were from the AVX high Q range. Component impedance measurements were made with a Keysight Technologies impedance analyzer. All rectifiers utilised a single Wolfspeed SiC Schottky diode, the C3D10065A, which has 10A forward current capability and 650V blocking voltage capability

To allow careful characterisation of rectifiers and to avoid the need of an inductive link and its associated instrumentation for testing the rectifier, a test rig was developed that reproduces IPT conditions in the tuned R _x coil when a rectifier is added at the receiver. With this test rig calculation of the efficiency of the receiver (n,Rx) and the input resistance of the rectifier under test as seen from the output of the inverter, is possible without affecting any other part of the IPT system.

The five implemented rectifiers were compared with respect to their efficiency and their effect on the inductive link. To ensure repeatability of results, a power sweep was performed in each experiment and measurements were recorded twice, when the output power was increasing from minimum to maximum and when the output power was decreasing from maximum to minimum. The results presented are the average. The test rig enables measurement of the combined impedance of the receiving coil, external tuning capacitor and the rectifier under test. At resonance, this impedance is equal to the equivalent series input resistance of the rectifier, Rin;ser. In the current driven case, Rin;ser is equal to Rin;s and in the voltage driven case Rin;ser is equal to the series transformation of Rin;p. When the rectifier is designed to reflect the optimal load this Rin;ser value is equal to Rac;ser independent of series or parallel tuning (which is equal to 10:6 in this case study).

Fig. 5a presents the measured n,R _X and Rin;ser for varying power (50W to 200W). Fig. 5b, Fig. 5c and Fig. 5d show the results of the variable Rdc experiments for Designs #2, #4 and #5 over a dc load range between 10% to 100%. At every dc load step, the Rin;ser of the topology and the residual reactance at the resonant tank (Xin;res) were calculated. Xin;res is the uncompensated reactance between the reactances of the Rx coil, the external tuning capacitor and the input reactance of the rectifier. To examine the inherent voltage regulation feature, the ratio between the output dc voltage to the current in the receiving coil (Vdc/iin) was calculated in Designs #4 and #5 and in Design #2 the ratio between the output dc voltage to the amplitude of the presented emf (Vdc/vin) was calculated. The experimental results are compared with time-domain SPICE simulations.

According to the plots in Fig. 5a, all designs showed low deviation in efficiency over the entire output power range. The worst case deviation in efficiency over Pdc was in Design #2 and was 4%. Designs #2, #3 and #5 exhibited deviations in Rin;ser lower than 3% from the nominal value while Designs #1 and #4 exhibited deviations of 7:2% and 9:4% respectively. Design #1 had the lowest capacitance across the diode amongst the implemented rectifiers and is therefore more sensitive to the variation of pn junction capacitance. Design #4 on the other hand, although having a significantly higher Cp, is more sensitive to variations in Xc than Design #1 due to the selection of Ar. A small variation in Ar, when it is greater than 1 :6, will result in a large variation of Qin and therefore in Rin;p. While Design #5, the current driven topology, operates in the same Ar region as Design #4, its Rin.ser profile over output power has a much lower deviation than Rin;ser of Design #4. This is because the capacitance across the diode in Design #5 is twice the magnitude of the respective capacitance in Design #4. Design #5 (the CDR) has the lowest n,R _X because the losses in its L are the highest amongst the five designs. Since all the designs, apart from Design #4, have the same Rdc, the inductors (L) in Designs #1 to #3 and #5 experience identical voltage waveforms over a cycle. Thus, the highest inductor current amongst the designs occurs in Design #5 causing the highest losses. Comparing the HVDR circuits, Designs #1 to #4, the higher the presented Rin;ser the higher receiving end efficiency was achieved. In general all the developed rectifiers presented an error in their Rin;ser proportional to the error between theoretical and experimental values of Rdc. Error in the experiment is larger for solutions where the diode parasitic capacitance is significant compared to the external capacitance across the diode and where the sensitivity of Qin to Ar is large. Hence, the greatest error was observed in Designs #4 and #5.

Figs. 5b & 5c show good agreement between simulation and experimental results. In simulations, the passive components were set equal to the measurements of the impedance analyzer. Designs #2, #4 and #5, performed as expected in that in Designs #4 and #5, Rin.ser decreased with Rdc and in Design #2, Rin;ser increased with Rdc. In terms of input reactance variation, Designs #4 and #5 presented residual reactances at the receiving end with magnitude smaller than 1 % of the impedance of the receiving coil, Xrx. Furthermore, in these two designs the output voltage was inherently regulated when the current in the receiving coil was kept constant. The output voltage was regulated within 3% and 8% of its initial value in Design #4 and in Design #5 respectively. Design #2 also exhibits some inherent output voltage regulation with a deviation of 25% for constant input voltage. To investigate further how the implemented rectifiers affect the efficiency of the inductive link and the reflected impedance at the transmitting coil, the measured values of Fig. 5b and Fig. 5d were mapped on the contour plots of Fig. 6. Figs. 6a, 6b and 6c show the contours of the inductive link efficiency (njink), the reflected resistance at the transmitting coil (Rref), and the reflected reactance at the transmitting coil (Xref) respectively. All contours of Fig. 6 are plotted as functions of the normalised resistance seen by the receiving coil, Rin;ser/Rac;ser, and the normalised residual reactance at the resonant receiving tank, Xin;res/XM. Note that Rac;ser is the ac resistance at the receiving end that provides the optimal link efficiency and XM is the impedance of the magnetising inductance between the coils forming the inductive link (which is 7.1 1 Ω at the frequency of operation). Moreover, the contours of ηπηΐ< and Rref are normalised to their respective optimal values. Finally, the contours of Xref are normalised to XM.

The trajectories of the normalised values of Rin;ser and Xin;res have been added to the contours plots of Fig. 6. Specifically, the experimental data of Designs #2 and #4 have been used as they both exhibit the desirable property of inherent voltage regulation for variable dc load and Design #4 also exhibits low deviation in input reactance with variation in dc load. As Design #5 behaves in the same way as Design #4 with regards to these parameters, only the data from Design #4 has been plotted in Fig. 6.

As shown in Fig. 6a, at 100% dc load all tested designs are within the n,iink.o _P t contour. As the load decreases down to 50%, all designs fall into lower efficiency contours but they are within 97% of the n,iink.o _P t. Although Design #2 is detuning the receiving coil at dc loads lower than 100%, the resultant link efficiency is actually slightly higher than that for Design #4 for the same load value. This occurs because Rin;ser of Design #2 increases from its initial value, rather than decreases as in the case of Design #4, where the link efficiency is more tolerant to the presence of residual reactance, as shown in the contours of Fig. 6a. At dc loads lower than 20%, the link efficiency in both designs falls below 90% of n,iink.o _P t, however the losses in the inductive link would be smaller in magnitude than the losses when maximum power is transferred at i jlink.opt. In Fig. 6b and Fig. 6c, the reflected impedance at the transmitting coil behaves inversely to the input impedance of the utilised rectifier. This is a basic property of inductive links. In Design #2, Rref decreases linearly as Rdc increases. On the other hand, in Design #4, Rref increases linearly as Rdc increases. In terms of reflected reactance (Xref ), in Design #2 the reflected reactance does not increase beyond 0: 15 times XM, despite the residual reactance at the receiving coil reaching six times XM. Comparing the magnitude of Xref for Design #2 to the impedance of the transmitting coil (XTX), Xref is always lower than 1 % of XTX and will not affect the tuning of the Tx coil. On the contrary, while Design #4 does not introduce a Xin;res greater than 25% of XM, the Xref for this design increases with Rdc and can reach almost three times the magnitude of XM.

The inherent output voltage regulation feature can be achieved in both Design #2 and Design #4. For Design #2 a constant output current at the T _x will result in a constant induced voltage in the R _x coil, thus providing the condition for the output voltage regulation feature. In Design #2 the transmitting resonant tank will not be affected by the variation of Rdc. Hence, since Rref decreases with Rdc, a constant output current Class-EF inverter will be compatible. In Design #4, inherent output voltage regulation occurs with a constant current in the R _x coil. This requires the variation of the magnitude of the induced voltage in the R _x coil and hence, the variation in the current in the T _x coil. Since the reflected impedance increases with Rdc a Class-D ZVS constant output voltage inverter will be capable to provide the conditions for inherent output voltage regulation

It will be understood that the above description of specific embodiments is by way of example only and is not intended to limit the scope of the present disclosure. Many modifications of the described embodiments, some of which are now described, are envisaged and intended to be within the scope of the present disclosure.

Class-E rectifiers of the type described herein can be used in any type of circuit that makes use of a resonant tank, for example wireless power applications including those which utilise inductive power transfer but also RF applications. Rectifiers of the type described herein may also be used within resonant power dc/dc converters, meaning they can in fact be used within any dc/dc converter application.

In the case of an IPT system power throughput control and inherent voltage regulation will be achieved when the transmitting coil is driven by a Class-D inverter (and particularly the zero-voltage Class-D inverter for maximum efficiency) since the resistance to the transmit coil increases with increasing the load resistance. A Class- D inverter is shown in Figure 13. As the load reflected at the transmitting coil increases with the output dc load of the rectifier (Rdc) a constant output voltage inverter is required such that the magnitude of the input source of the rectifiers remains constant. In the IPT case the magnitude of the input source of the rectifier is dependent upon the current in the receiving coil. With a constant magnitude source for the rectifier the aforementioned rectifier properties can be applied. In the case of resonant dc-dc converter applications inherent output voltage regulation will be achieved if a load-independent Class-EF inverter is used in combination with any of the Class-E rectifiers of Figs. 2a-d when the rectifiers are designed with an Ar between 1.75-2. Because the inverter has a constant current output, the magnitude of the input source of the rectifier will remain constant and from the low input reactance deviation and monotonic input resistance properties of the Class-E rectifiers voltage regulation will be possible.

A schematic circuit diagram of a suitable inverter in shown in figure 7. The inverter 700 is based on a class E inverter, and more particularly is based on a class 'EF' inverter. In operation, the inverter 100 converts direct current (DC) from a power source 702 to alternating current (AC).

The inverter 700 incorporates a transistor 706. The transistor 706 may be a metal- oxide-semiconductor field-effect transistor 706 (MOSFET) as is known in the art. Figure 1 shows an n-channel MOSFET. The transistor 706 is coupled to a first inductor 704 having a first inductance Li. The first inductor 704 is coupled to the transistor 706 via a first transistor node, which, in the case that the transistor 706 is an N-channel MOSFET as in Figure 1 , will be the 'drive' node. The first inductor 704 is in turn coupled to a power source 702, which is arranged to provide a DC input signal to the inverter 700. The transistor 706 is also coupled to ground 708 via a second node which, in the case that the transistor 706 is an n-channel MOSFET, will be the 'source' node. Finally, the transistor 706 is switched on / off via a third transistor node which, in the case that the transistor 706 is an n-channel MOSFET, will be the 'gate' node. The transistor 706 can be switched on/off by applying an input from, for example, a signal generator (not shown). Typically, the signal generator produces a square wave input signal.

A first capacitor 716 having a first capacitance Ci is connected in parallel with the transistor 706, between the first inductor 704 and ground 708. It will be appreciated that capacitor Ci allows the inverter 106 to operate in a ZVS mode. The voltage on Ci naturally falls to zero twice per cycle and these two events are the point where the transistor changes state. Thus, it is the function of the complete circuit (all the components operating together) that gives rise to these zero volt instances. The existence of the capacitor C1 means there is a finite rate of change of voltage across the transistor giving a finite time for it to change state.

A resonant circuit 710 is also connected in parallel between the first inductor 704 and ground 708. The resonant circuit 710 has a second inductor 712 having an inductance l_2, and a second capacitor 714 having a second capacitance C2. The resonant circuit 710 has a resonant frequency FT, which is dependent on the values of C2 and l_2 as will be appreciated by those skilled in the art.

In embodiments of the present disclosure, the resonant circuit 710 is designed to have a resonant frequency Ft which is a non-integer multiple of the transistor 1206 switching frequency F _sw . Preferably, the non-integer multiple is between 1 and 2, is more preferably between 1 .5 and 1 .65, and is even more preferably equal to 1 .5. A third capacitor 718 having a third capacitance C3, a third inductor 718 having a third inductance L3, and a transmitter coil (not shown) are also connected in parallel with the transistor 706 and the first capacitor 716. The resistance of the transmitting coil forms part of the resistive load 722 of the inverter 100. In operation, the resistive load 722 of the inverter 700 is also increased in accordance with the respective resistive loads of any receiver coils within the IPT system. These respective receiver loads are 'reflected' to the transmitter coil when the IPT system is in operation, as will be understood by the skilled person. The value of the load may depend on the turns ratio and coupling factor, and can be considered to include the loss resistance of the receiver coil. It will thus be understood that the resistive load 722 experienced by the inverter 700 can vary as the receiver coils change in number, orientation, size or distance from the transmitter coil.

In the circuit of figure 1 , I in is the steady input current. A significant DC component with little current ripple is expected. I ₀ is the sinusoidal output current that flows in the transmit coil.

In operation, the power source 702 supplies a DC input signal to the inverter. The transistor 706 is switched on and off at a switching frequency F _sw . This has the effect of producing an AC output signal, which passes through the load. As the AC current passes through the transmitter coil, a time-varying magnetic field is produced.

As will be appreciated by those skilled in the art, switching the transistor 706 on or off whilst a non-zero current or voltage is passing through the transistor 706 gives rise to switching losses through the transistor 706, in accordance with the well- known equation P=IV; where P is the loss of energy in the transistor 106 per second, I is the current passing through the transistor 706 and V is the voltage across the transistor 706.

The resonant circuit 710, which has a resonant frequency which is a non-integer multiple of the switching frequency, acts to keep the current flowing through the transmitter coil constant, as will be described in more detail below.

It will be appreciated that other types of inverter can be used with Class-E rectifiers described herein, for example Class-D inverters and Class-E inverters.

Figure 10 shows a Class-D inverter 1300. The invertor comprises a voltage source 1002. The Class-D inverter comprises a half-bridge configuration. The half-bridge circuit consists of an upper and a lower switch, for example two MOSFET switches 1006a, 1006b. The switches 1006a and1006b can be driven by an external signal as would be understood by the person skilled in the art. The half-bridge configuration is connected with a series tuned inductor capacitor network 1010 comprising a capacitor 1014 having a capacitance C and an inductor 1012 having an inductance L. The Class-D inverter 1000 also comprises an ac load resistor 1022. In the case of a resonant converter the ac load resistor 1022 is represented by the input terminals of the rectifier (with the addition of the input reactance of the rectifier) and in the case of an inductive power transfer system the ac load is the reflected resistance from the receiving resonant tank.

The conventional operation of a Class-D inverter 1000 requires the resonant network of the inverter, e.g. the inductor 1012 and capacitor 1014 at the output of the inverter, to be at resonance at the frequency of operation. In other words, prior Class-D circuits have always been designed such that the operating frequency / switching frequency is an integer multiple of the frequency of operation.

However, by changing the resonant frequency of the inductor-capacitor network 1010 such that it is away from the operating frequency, the inverter can output a constant amplitude current at the operating frequency. In other words, the resonant network is designed such that it has a resonant frequency which is a non-integer multiple of the switching frequency / operating frequency. This allows the inverter to operate with a substantially constant current passing through the load resistance, even as the load varies. To achieve constant output current in this manner, the ac load resistance should also be smaller than the residual reactance of the inductor- capacitor network 1010 at the frequency of operation. When operating away from resonance it is beneficial to have an inductive residual reactance from the inductor-capacitor network at the frequency of operation as an inductive residual reactance contributes in the elimination of turn ON losses in the transistors of the half-bridge while the turn OFF losses in the transistors can be adjusted based on the magnitude of the reactance. The class-D inverter 1000 can be designed to give constant current as the rectifier load resistance increases, if the circuit is tuned such that the inverter 1300 drives a residual inductance at the operating frequency. This can be achieved using class-E rectifiers having an A _r value between 1 .75 and 3.

Figure 9 shows a Class-E inverter 900. The Class-E inverter 900 comprises a switching device such as a transistor 906. The transistor 906 is connected in parallel with a capacitor 914a and an output load network. The transistor can be turned on and off by an external signal. The external signal may be provided, for example, by a gate drive circuit. The gate drive circuit typically comprises further transistors which are capable of providing the required amount of charge to the gate capacitance of the transistor of the power circuit. The transistors within the gate drive circuit are controlled by a digital, i.e. small, signal, which could be provided by, for example, a microcontroller. The output load network is formed by the series combination of an inductor 912a and a capacitor 914b and an ac load resistor 922. The inverter 900 has a current input which is provided by the series connection of a voltage source 902 and an inductor 912b. The ac load resistor 922 is represented by either the input terminals of the rectifier in resonant power converter applications or by the reflected resistance of the receiver in inductive power transfer systems.

In the conventional operation of a Class-E inverter 900, the passive components of the circuit are evaluated such that the transistor 906 experiences zero voltage when it turns ON and OFF (ZVS), and zero voltage derivative when it turns ON (ZDS). However, surprisingly, it has been found that by relaxing the last constraint of zero voltage derivative, while keeping ZVS, and designing the inverter 900 such that the derivative of the voltage across the transistor 906 when it turns ON is negative, the amplitude of the current in the output load network, the series combination of an inductor-capacitor 912a, 914b and an ac load resistor 922, has a small deviation as the output ac resistor decreases from its initial value. The derivative is a time derivative, and can be thought of as the rate of change of the voltage. The greater the magnitude of the transistor voltage derivative, the lower the deviation in the magnitude of the current through the output load network. In other words, the class-E inverter can be designed to give an approximately constant current by relaxing the condition on zero derivative switching.

Further advantages of the presently disclosed rectifier and inverter arrangements will now be discussed.

Having a low deviation input reactance with varying output load is advantageous for IPT and resonant converter applications since the resonant tank in the system (e.g. a receiving end of an IPT or the output of the inverter in a resonant converter) will always experience the same reactance from the input terminals of the rectifier. This is because when a rectifier is added to an inductive link, it will introduce some reactance to the resonant tank at the receiving end of the link. The resonant tank consists of the receiving coil and the tuning capacitor. The tuning capacitor value will take into account the reactance presented by the rectifier. The sum of the reactances of the receiving coil, tuning capacitor and the reactace of rectifier should equal to zero, i.e. resonate at the frequency of operation. When the dc load of the rectifier changes, the presently disclosed arrangeent ensures that the input reactance will deviate insignificantly, such that the sum of reactances will remain zero. Cancelling out the reactance of the receiving coil (or tuning the coil) means that high link efficiency can be achieved.

Further to the low input reactance deviation property, at the A _r range between 1 .75 to 3 the topologies of the present disclosure present an inherent voltage regulation with varying Rdc if the amplitude of the input source remains constant. Therefore, additional control circuitry for voltage regulation can be removed, improving end-to- end efficiency and reducing PCB real estate requirements.

The Class-E operating mode of the present disclosure does not detune the resonant tank(s) of the system when the output dc resistance increases. Furthermore, at this operating mode, inherent voltage regulation is achieved by the rectifier making the circuit independent of control and energy storage components. These are two features that significantly improve the real world performance of IPT systems and resonant power converters. As discussed above, prior arrangements suffered from the problem of a variation in the Class-E rectifier's input reactance as the dc load of the system changes. A Class- E rectifier designed with an Ar within the range of 1 .75 to 3 compresses the variation of its input reactance as the duty cycle decreases. Although it will introduce some reactance to the circuit that is going to be connected with, this reactance can be absorbed in the resonant tank that provides the sinusoidal input for the rectifier, e.g. the receiving end of an inductive link or the output of an inverter in a resonant dc/dc converter. As the deviation in the input reactance of the Class-E rectifier will be low when the duty cycle changes, the resonant tank will not be affected because it is already compensating for the same reactance. Class-E rectifier designs at different Ar values will present reactances with magnitude that is dependent on the duty cycle and will hence affect the resonant tank used to provide the sinusoidal input for the rectifier since the tank can only compensate for a specific reactance. As also discussed above, it has proved difficult in prior systems to regulate the output voltage of the system. The input resistance of a Class-E rectifier designed with an Ar within the range of 1 .75 to 3 has a monotonic behaviour as the duty cycle decreases due to the increase of the output load (Rdc). This monotonic input resistance behaviour along with the low deviation in input reactance result in the decrease of the power extracted by the input source when Rdc increases; assuming the magnitude of the source remains constant. This decrease of extracted power from the source results in the current delivered to the output load (Rdc) to be proportional to the magnitude of Rdc. Therefore, the output voltage is inherently regulated as the output dc load increases.