Title:
WIRING STRUCTURE, SEMICONDUCTOR DEVICE, METHOD FOR OPERATING ACTIVE ELEMENT, METHOD FOR MANUFACTURING WIRING STRUCTURE, METHOD FOR USING WIRING STRUCTURE, AND METHOD FOR CONTROLLING WIRING RESISTANCE OF WIRING STRUCTURE
Document Type and Number:
WIPO Patent Application WO/2020/179097
Kind Code:
A1
Abstract:
This wiring structure (1) of the present disclosure comprises: a wiring layer (10) that has a metal element as a main component, and extends in one direction; a metal layer (20) that opposes the wiring layer (10); and a solid electrolyte layer (30) that is positioned between the wiring layer and the metal layer, and is formed to wrap the wiring layer in cross sectional view when cut at least in a plane orthogonal to the one direction. The wiring layer and the metal layer are electrically insulated with the solid electrolyte layer interposed therebetween.
Inventors:
NISHIKAWA ASAMI
SHIBATA SATOSHI
NISHITANI YU
ASANO TETSUYA
TSUJITA TAKUJI
SUGIMOTO YUTA
SHIBATA SATOSHI
NISHITANI YU
ASANO TETSUYA
TSUJITA TAKUJI
SUGIMOTO YUTA
Application Number:
PCT/JP2019/026877
Publication Date:
September 10, 2020
Filing Date:
July 05, 2019
Export Citation:
Assignee:
PANASONIC IP MAN CO LTD (JP)
International Classes:
H01L21/3205; H01B1/06; H01B7/00; H01L21/768; H01L23/532
Foreign References:
| JP2015012049A | 2015-01-19 | |||
| JP2017199825A | 2017-11-02 | |||
| JP2017212260A | 2017-11-30 | |||
| JP2017042734A | 2017-03-02 | |||
| JP2014031558A | 2014-02-20 |
Attorney, Agent or Firm:
NII, Hiromori et al. (JP)
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