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WO/1990/003630A1 |
A card (20) has a recording surface (36) with three aligned horizontal rows (40, 42, 44) of boxes. The first row (40) is in the middle with the second row (42) above it and the third row (44) below it. An initial odometer reading of a ve...
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WO/1990/002381A1 |
A hierarchical or feedback neural network is formed by subjecting time sharing analog input signals and weight data, which are inputted sequentially via analog signal buses, to sum/product operation, and using an analog neuron processor ...
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WO/1989/012280A1 |
An analog operation circuit adapted to operating multiplication, division, compression, elongation, and combinations thereof. In order to realize the circuit in the form of MOS LSI overcoming the problems inherent in the existing analog ...
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WO/1989/006403A1 |
A high-speed analog multiplier circuit (Figs. 3-6) for multiplying two analog inputs (X, Y) comprises a signum generator (21) having an X input multiplier (at 26, 27) and having an output connected to a high-speed electronic switch (22)....
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WO/1989/004949A2 |
A monolithic interface circuit for use with a linear variable differential transformer (LVDT) position transducer. The interface circuit includes a drive circuit for providing an excitation signal of selectable frequency and amplitude to...
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WO/1989/002192A1 |
A time-multiplexed switched capacitor circuit in which certain capacitors are shared during local time periods of a global time period to allow the total capacitance of the circuit to be reduced. Corresponding savings in chip area in an ...
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WO/1989/002189A1 |
A D.C. stabilized logarithmic amplifier, which in response to an input video signal Vin having blank and picture intervals provides a temperature compensated logarithmic signal Vout(comp). The logarithmic amplifier cell (16) has first an...
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WO/1989/000739A1 |
A multiphase multiplier circuit employs analog switches, each of which is duty controlled for multiplying input voltage signal with a multiplier determined depending on the duty cycle of ON/OFF period. The multiphase multiplier circuit f...
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WO/1988/010476A1 |
A neural network includes a feature representation field which receives input patterns. Signals from the feature representation field select a category from a category representation field through a first adaptive filter. Based on the se...
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WO/1988/007131A1 |
A mass flow fuel injection control system is provided for an internal combustion engine and measures mass and flow velocity of combustion air. The length of fuel injection pulses is determined by formula (I), where PD is the air pressure...
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WO/1988/006770A1 |
A CMOS analog multiplying circuit comprising a first transistor (1) having its current electrodes coupled between a first reference voltage line and a first node and its gate electrode coupled to a first input node having, in use, an inp...
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WO/1987/007944A1 |
Opto-electronic scale reading apparatus comprising a read head (10) in which a plurality of optical emitter and receiver pairs (15, 25) are arranged so that beams (13) of collimated light generated by the respective emitters (15) fall on...
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WO/1987/007943A1 |
In one preferred embodiment, apparatus for determining values of a periodic function by interpolation receives signals A, B, C, D from the periodic function which are nominally in phase quadrature with each other. These are combined to p...
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WO/1987/003437A1 |
A digital-to-analog converter which develops an analog output representative of the difference between two digital inputs represented by the rates of two series of pulses. A prescribed number of pulses of each series is counted (12) to d...
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WO/1986/006524A1 |
In order to rapidly calculate the dose, particularly of food for a baby or an adult, and the dose of a drug for the treatment of a patient, a ruler according to the present invention is used which is comprised of a fixed sector (1) and a...
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WO/1986/006189A1 |
A control circuit comprises AGC circuits (2, 3) that receive x-input signal, and a gain control amplifier (1) that receives z-input signal. Gain of the gain control amplifier (1) is controlled by a gain control voltage (7) produced by th...
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WO/1986/005267A1 |
An area gauge consisting of a transfer portion composed of a transfer screw (1), an adjusting screw (7), and a regulator member (22) provided with a swivel ring (25) via a shaft, a measuring portion composed of a gauge body (16), a gauge...
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WO/1986/001657A1 |
An integrator that is useful in forming low pass, band pass, high pass, and band stop filters. The integrator (10) comprises a transconductance amplifier (20) and a capacitor (65) which is connected between the amplifier output terminal ...
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WO/1986/001020A1 |
The apparatus comprises rotatable superimposed discs (3, 4, 5, 6) mounted on a base (2). The discs bear first indicia - for example, numbers - and the base a marker (10). In use of the apparatus, the user selects a particular sequence of...
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WO/1986/000480A1 |
An adaptive hybrid circuit is coupled between a transmitter (19) and a receiver (21) in a local station (9) coupled to a transmission line (11) in a local area network. An output signal from the receiver (21) together with a transmit sig...
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WO/1985/003392A1 |
An integrated circuit (100) for squaring an original input signal (VIN) includes a pair of dual-ended difference amplifiers (110, 120) to each of which the input signal is delivered, a pair of dual-to-single-ended converters (130, 140), ...
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WO/1985/001622A1 |
A common mode detector (10) for producing an output voltage (VA + VB)/2 in response to input voltages VA and VB contains a pair of MOS transitors (MA and MB) connected in series between a pair of input terminals A and B to which the inpu...
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WO/1985/000497A2 |
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WO/1984/002992A1 |
A system to perform non-spectral analysis and synthesis of a complex waveform. The sensor signal (30) is applied to preamplifier (60) and then to logarithmic analog to digital (LAD) convertor (40). The converted signal is differentiated ...
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WO/1984/001244A1 |
Apparatus for converting an analog-format electrical signal or quantity (such as the magnitude of an electrical circuit element) into a corresponding pulse-format signal, preferably in the form of a train of periodic pulses the lenghts o...
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WO/1984/001065A1 |
A switched capacitor parasitic insensitive integrator comprises an operational amplifier (6), an integrating capacitor C2, a switched capacitor C, and four switches, two of even phase E1, E2 and two of odd phase 01, 02. In order to minim...
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WO/1983/001852A1 |
Method for comparison between a first optical signal (PHI1) and at least one other signal. The invention can for instance be used for image recognition. In this application it is a problem to be able to perform parallel processing of the...
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WO/1982/001949A1 |
A squarer comprising an electric heater (1) thermally contacting one of the working surfaces of a cooling means (2), that working surface also contacting thermally the first sensitive element of a differential temperature sensor (4). The...
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WO/1982/001253A1 |
A watt/var transducer utilizing the pulse width-pulse height modulation type of multiplying scheme wherein a stable squarewave is generated by switching from one reference voltage to another reference voltage, the output thereof is integ...
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WO/1982/000536A1 |
A stage converter of electric signals comprises a circuit (1) with variable gain factor, the controlling inputs of which are connected to the outputs of a generator (3) of controlling signals to ensure variation of the gain factor of the...
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WO/1981/002638A1 |
Method and apparatus for determining the heat loss of for instance a human or a heated building depending upon the current climate. The principle is based upon an analogue method of simulation and includes a heated climate sensing body. ...
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WO/1981/001762A1 |
A quadrature frequency converter comprises two circuits (5, 6) with variable gain factor, each of them being connected to circuit (7, 8) for reversing the sign of the gain factor. The absolute value of the gain factor of the converter de...
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WO/1981/000774A1 |
Multiple redundant sensor signals (10, 11, 12) are processed through an equalizing (20, 21, 22) and selecting (46, 100) network which outputs the midvalue signal and eliminates all null offsets occurring among signals. Errors due to drif...
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WO/1981/000497A1 |
A function generator as for use in a system of compatible quadrature AM stereo approximates the tangent function curve, allowing for the provision of essentially undistorted intelligence signals, A form of differential amplifier, includi...
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WO/1980/000497A1 |
An arrangement for generating amplitude-modulated, ultrasonic transmission pulses comprising at least a switching circuit (4) provided with an inductive load (12) for generating the transmission pulses and controlled with a plurality of ...
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WO/1980/000201A1 |
Circuit (10) for generating an error voltage (26) which is proportional to the difference between a desired value of a physical parameter and the actual value of the physical parameter. The circuit (10) operates by alternately switching ...
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WO/1979/001119A1 |
Apparatus for tracking the peak of a correlation function between two signals (x(t),y(t)) includes a coarse peak detector (26) for providing a coarse measure of the peak position and a tracking correlator for providing a fine indication ...
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WO/1979/001079A1 |
An improved variometer comprises a needle indicating on a graduation the instantaneous speed hx of the aerodyne, and a speed representative of the potential speed h T. The instantaneous vertical speed hx is obtained by means of a circuit...
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WO/1979/000072A1 |
An interlock mechanism for an operating system such as a zoom lens with at least first and second independently controllable operating parameters comprising sending means (11, 12) for generating control outputs which are the logarithmic ...
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JP2024521006A |
Numerous embodiments are disclosed for an output circuit for an analog neural memory in a deep learning artificial neural network. In some embodiments, an output block receives a current from a W+ bit line and a current from an associate...
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JP7488005B2 |
A magnetic double tunnel junction (MDTJ) (which, preferably, has a large aspect ratio, wherein length L of the MDTJ>>width w of the MDTJ) has magnetic domain wall(s) or DW(s) in the free layer of the MDTJ, wherein controlled movement of ...
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JP2024065809A |
The present invention generates an output signal that appropriately includes feature information included in an input signal. A reservoir calculation device includes a reservoir circuit and an output circuit. The reservoir circuit is sup...
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JP7483858B2 |
A semiconductor device that implements artificial neurons and synapses together on the semiconductor device includes a plurality of fins formed on the semiconductor device, and a plurality of gates formed around the plurality of fins to ...
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JP2024065044A |
An object of the present invention is to provide a method for operating a semiconductor device that suppresses variations in calculation results. A method of operating a semiconductor device having first and second cell arrays and first ...
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JP2024519264A |
The present invention comprises a solution comprising reverse micelles (14) in contact with each other to form a lipid bilayer (13) at the points of contact, wherein at least a portion of the points of contact are formed by reverse excha...
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JP7480133B2 |
A semiconductor device capable of performing arithmetic operation with low power consumption is provided. The semiconductor device includes first and second circuits, a first amplifier circuit, first to fourth switches, and a capacitor, ...
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JP7480391B2 |
A memory device for CIM, applicable to a 3D AND-type flash memory, includes a memory array, input word line pairs, and a signal processing circuit. The memory array includes first and second pairs of memory cells. Each first pair of memo...
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JP2024061728A |
The present invention provides a semiconductor device capable of performing sum-of-products operations with low power consumption. [Solution] A semiconductor device having first and second circuits, the first circuit having a first holdi...
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JP2024518884A |
A number of embodiments are disclosed for dividing an array of non-volatile memory cells in an analog neural memory into multiple parts in a deep learning artificial neural network. Each portion of the array interacts with specific circu...
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JP7474870B2 |
Numerous embodiments of analog neural memory arrays are disclosed. Certain embodiments contain improved mechanisms for pulling source lines down to ground expeditiously. This is useful, for example, to minimize the voltage drop for a rea...
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