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WO/2014/139151A1 |
Embodiments of the invention are generally directed to a line driver with separate pre-driver for feed-through capacitance. An embodiment of an apparatus includes a differential pair of transistors to generate an output signal on a first...
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WO/2014/145066A2 |
Systems and methods for operating transistors near or in the sub-threshold region to reduce power consumption are described herein. In one embodiment, a method for low power operation comprises sending a clock signal to a flop via a cloc...
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WO/2014/146016A2 |
A multiple output current stimulator circuit with fast turn on time is described. At least one pair of input side and output side transistors is arranged in a current mirror connected to a supply transistor by cascode coupling. The outpu...
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WO/2014/143206A1 |
Timer circuitry completely formable in an integrated circuit (IC) for generating a clock signal in an implantable medical device is disclosed. The timer circuitry can be formed on the same Application Specific Integrated Circuit typicall...
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WO/2014/143046A1 |
Systems and methods for transpositional modulation and demodulation are provided. One such method for generating a signal includes the steps of providing a look-up table having a plurality of quarter-cycle waveforms, each of said quarter...
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WO/2014/140565A1 |
An assembly (100, 220, 300) that includes a laser diode (110, 310) and a driver circuit (120) that operates to give the assembly an (100, 220, 300) adjustable impedance. The driver circuit (120) adjusts impedance by repeatedly alternatin...
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WO/2014/138033A1 |
Certain aspects of the present disclosure provide a voltage level shifting circuit employing a low latency, AC-coupled voltage boost circuit, as well as other circuits and apparatus incorporating such a level shifting circuit. Such level...
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WO/2014/137736A1 |
Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related method are disclosed. In one embodiment, a single clock source is provided for the 3DIC and distributed to elements within the 3DIC. Delay is pr...
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WO/2014/136399A1 |
An injection-locked oscillator (100) is provided with: a ring oscillator in which a first amplification circuit (141) that comprises an N-channel MOS transistor (111) and P-channel MOS transistors (112, 113) and a second amplification ci...
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WO/2014/137714A1 |
A particular method includes receiving a retention signal (nret). In response to receiving the retention signal, the method includes retaining state information (q internal, 310) in a non-volatile stage (302) of a retention register (300...
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WO/2014/137666A1 |
A system includes first circuitry including first elements for operating in a low power mode; second circuitry including second elements for operating in a high-temperature mode; and one or more switching elements for selecting between t...
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WO/2014/130174A1 |
A clock multiplier circuit (200) includes a clock generator (210), a delay element (220), a logic gate (230), and a duty cycle correction circuit (240). The clock generator (210) generates a clock signal (X). The delay element (240) gene...
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WO/2014/130754A1 |
A numerical controlled oscillator generating an output signal with a digital clock signal having a variable frequency is disclosed. The numerical oscillator is controlled by a programmable numerical value being subject to a transfer func...
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WO/2014/130561A1 |
In an embodiment, a flip-flop circuit contains a 2-input multiplexer (102), a master latch 9104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determine whether data or scan...
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WO/2014/130560A2 |
A method is provided for implementing a timer using a floating-gate transistor. The method includes: injecting a charge into a floating-gate transistor at an initial time, where a gate terminal of the floating-gate transistor is comprise...
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WO/2014/124037A1 |
In an embodiment of the invention, a flip-flop circuit (100) contains a 2-input multiplexer (102), a master latch (104), a transfer gate (106) and a slave latch (108). The scan enable control signals SE and SEN of the multiplexer determi...
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WO/2014/124023A1 |
One feature pertains to an integrated circuit "IC" that includes a first plurality of ring oscillators (318) configured to implement, in part, a physically unclonable function "PUF". The IC further includes a second plurality of ring osc...
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WO/2014/120416A2 |
A divide-by-two divider circuit receives a differential input signal and outputs four rail-to-rail, twenty-five percent duty cycle signals, where the frequency of the output signals is half of the frequency of the input signal. Each latc...
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WO/2014/116100A1 |
An on-chip controller for SSL driver (101) that includes control circuitry comprising Bipolar, CMOS and DMOS power devices on a single monolithic substrate is provided. The SSL driver control circuitry (101) includes a sensing stage and ...
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WO/2014/111328A1 |
The invention relates to a high-voltage pulse generator, in which the high-voltage pulses provided are transformed to a higher voltage level by means of a transformation network (3-i) before being coupled into a coaxial conductor arrange...
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WO/2014/111274A1 |
The invention relates to a pulse generator, preferably an inductive voltage adder, in which the energy is coupled purely inductively into the cavity (3) between the outer conductor (1) and the inner conductor (2). The inductive coupling ...
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WO/2014/111229A1 |
The invention relates to a device and a method for generating high-voltage pulses by means of high-voltage pulse generator stages (6R-i) which are inductively decoupled from one another and each of which inductively couples high-voltage ...
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WO/2014/110371A1 |
A single-ended comparator is disclosed herein. The comparator may be implemented with low-voltage semiconductor devices that are capable of operating with high-voltage signals at an input. The single-ended comparator may be integrated in...
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WO/2014/110566A1 |
A magnetic tunneling junction non-volatile register with feedback for robust read and write operations. In an embodiment, two MTJ devices (124; 126) are configured to store a logical 0 or a logical 1, and are coupled to drive an output n...
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WO/2014/094506A1 |
Disclosed is a small-sized rapidly-flip-flop Schmitt flip-flop circuit used for a silicon-on-insulator process, which changes the threshold voltage of a MOS transistor by adopting a PMOS/NMOS control circuit, so as to enable the input tr...
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WO/2014/094515A1 |
A discharge system for liquid phase pulses output in a time-delay manner based on multiple switches, comprising: a master circuit unit composed of n stages of discharge circuits and a drive unit. The drive unit is used for successively o...
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WO/2014/098558A1 |
The present invention generally pertains to a pulse generator (100) and a method for producing pulse, more particularly the present invention pertains to a constant pulse width generator and a method for producing constant pulse width si...
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WO/2014/092819A1 |
A quantum information processing system includes a waveguide having an aperture, a nonlinear quantum circuit disposed in the waveguide and an electromagnetic control signal source coupled to the aperture. The present invention relates to...
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WO/2014/082469A1 |
Provided is a high-voltage device of a composite structure, comprising: a high-voltage power MOS transistor (HVNMOS)and a JFET, wherein the high-voltage power MOS transistor (HVNMOS) comprises a drain electrode, a source electrode, a gat...
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WO/2014/080272A1 |
An apparatus to generate random numbers from radioactive decay, comprises at least a source of radioactivity and a radioactivity sensor to detect the radioactive decay of the source of radioactivity, the source of radioactivity (11) is i...
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WO/2014/073374A1 |
To provide a semiconductor device in which power consumption can be reduced and operation delay due to a stop and a restart of supply of power supply voltage can be suppressed and a driving method thereof. A potential corresponding to da...
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WO/2014/066402A1 |
In various embodiments, an integrated circuit is disclosed. In one embodiments, the integrated circuit comprises a first contact area from a first logic cell and a second contact area from a second logic cell. The second contact area com...
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WO/2014/062982A1 |
Exemplary embodiments are directed to power path switching between multiple charging ports of an electronic device. A device may include a charging port of a plurality of charging ports for coupling to a power supply via an over-voltage ...
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WO/2014/062983A2 |
Exemplary embodiments are directed to systems, methods, and devices for generating quadrature clock signals. A device may include a plurality of dynamic logic cells and a plurality of inverters. Each inverter of the plurality of inverter...
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WO/2013/063021A9 |
A hysteretic power converter (100) constituted of: a switched mode power supply (40); a hysteretic comparator (20), a first input (FB) of the comparator arranged to receive a feedback signal providing a representation of the output volta...
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WO/2014/048340A1 |
Provided is a device for testing the response characteristic of a metal oxide sample under steep-front pulses, comprising: a steep-wave-front current pulse generating device for generating a steep-wave-front current waveform; and a test ...
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WO/2014/043856A1 |
A clock-gating circuit is disclosed that may reduce unnecessary power consumption associated with clock distribution networks. For some embodiments, the clock-gating circuit includes a latch control circuit, a storage latch, and a logic ...
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WO/2014/044510A1 |
The invention relates to an identification circuit (1) for generating a unique identification pattern for an object to be identified, the circuit having: at least one bistable closed circuit ring (2) which consists of a plurality of swit...
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WO/2014/044493A1 |
The invention relates to a method for generating a random bit, having the following steps: providing a combinatorial multiplication device (2) for multiplying two input words (A, B) into an output word (C), comprising at least two inputs...
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WO/2014/041276A1 |
The invention concerns a high power pulse generator, belonging to the LTD family, comprising two series of power modules, one series of standard modules (3s) and one series of modified modules (3m), each comprising a switch (6s; 6m), pro...
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WO/2014/039226A1 |
A method and apparatus is disclosed herein for testing of multiple ring oscillators. In one embodiment, the apparatus comprises at least one ring oscillator structure having a ring oscillator having an inverter chain with an odd number o...
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WO/2014/028302A2 |
Systems and methods are provided for applying flux to a quantum-coherent superconducting circuit. In one example, a system includes a long-Josephson junction (LJJ), an inductive loop coupled to the LJJ and inductively coupled to the quan...
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WO/2014/008001A1 |
An oscillator is disclosed that can generate an oscillation signal using a latch and two delay elements. For some embodiments, the oscillator includes an SR latch, a first delay element, and a second delay element. The SR latch has a fir...
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WO/2014/006447A1 |
A phase switchable bistable memory device comprising a bistable memory component and a phase switching component is described. The bistable memory component comprises a bistable memory stage arranged to receive an input signal and a stat...
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WO/2014/006437A1 |
A digital sample clock generator (SCG) for generating a sample clock signal (SCLK) from an input signal (FD) derived from a drive measurement voltage signal (DMV) of a vibrating MEMS gyroscope (VMEMS) is described. The sample clock gener...
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WO/2014/004053A1 |
Disclosed is a differential clock signal generator (100) which processes a first differential clock signal (101) using a combination of differential and non-differential components to generate a second differential clock signal (111). Sp...
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WO/2013/191816A1 |
Various embodiments of a thermal control methodology and apparatus are disclosed. In one embodiment, an integrated circuit includes one or more thermal sensors, comparison circuitry, and control circuitry. The comparison circuitry is con...
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WO/2013/192327A1 |
Temperature-independent delay elements and oscillators are disclosed. In one design, an apparatus includes at least one delay element, a bias circuit, and a current source. The delay element(s) receive a charging current from the current...
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WO/2013/184596A1 |
One example embodiment may include a power supply system. The power supply system may include a main capacitor and a boost converter. The main capacitor is used to generate an electrical pulse. The boost converter is configured to be cou...
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WO/2013/177759A1 |
A CMOS D-type flip flop (D-FF) exhibits reduced power consumption by selectively disabling certain charging/discharging operations at specific circuit elements to minimize the capacitance of the circuit's internal nodes using a partial s...
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