Title:
【発明の名称】高性能D―A変換構造を提供する方法および装置
Document Type and Number:
Japanese Patent JP2001505732
Kind Code:
A
Abstract:
High-speed and high accuracy digital-to-analog (D/A) converters find many applications in signal processing. For wideband telecommunication systems, there is a strong demand on high-performance D/A converters. With the design of the present invention it is enabled to prevent distortions and intermodulations for high-speed and high-accuracy digital-to-analog (D/A) converters for telecommunication applications, where the requirements on distortion and intermodulation can be very stringent. By combining segmentation for MSBs and binary weighting for LSBs a high-performance digital-to-analog conversion architecture can be achieved, where a delay for the binary weighted LSBs is used to equalize a delay introduced by segmentation and where all bit switches (14) are clocked with a tree-like-clock distribution network (11). New floor plans for CMOS, BiCMOS and bipolar implementation are thus invented and circuits for CMOS bit switches and current sources are also disclosed.
Inventors:
Tan, Nianxion
Application Number:
JP52127598A
Publication Date:
April 24, 2001
Filing Date:
October 07, 1997
Export Citation:
Assignee:
Telefon Acty Boraget Elm Ericson (Pubble)
International Classes:
H03M1/06; H03M1/68; H03M1/08; H03M1/74; (IPC1-7): H03M1/68
Attorney, Agent or Firm:
Akira Asamura (3 outside)