Title:
【発明の名称】集積回路テスタ用のプログラム可能なフォーマッタ回路
Document Type and Number:
Japanese Patent JP2001514391
Kind Code:
A
Abstract:
A formatter circuit for channel of a multiple channel integrated circuit tester includes a drive control circuit, a compare circuit, and a random access memory (RAM). The RAM converts each value of input format selection data to corresponding format control data supplied to the drive control and compare circuits. The drive control circuit generates a set of drive control signals which determine the state of a test signal the tester channel supplies to a terminal of a device under test (DUT). The compare circuit determines whether a DUT output signal at the terminal is of an expected logic state. The drive and compare circuits employ multiplexers controlled by the format control data output of the RAM to select from among a variety of alternative data sources referencing desired states of the drive control signals or expected states of the DUT output signals. The formatter architecture permits flexible use of input reference data to provide a wide variety of selectable drive and compare formats.
Inventors:
Arkin brian jay
Application Number:
JP2000508018A
Publication Date:
September 11, 2001
Filing Date:
August 20, 1998
Export Citation:
Assignee:
Creedance Systems Corporation
International Classes:
G01R31/319; G01R31/28; G11C29/56; G11C29/38; (IPC1-7): G01R31/28; G01R31/319
Attorney, Agent or Firm:
Kunio Yamaguchi (1 person outside)