Title:
【発明の名称】組合されたプログラム可能論理アレーとアレー論理
Document Type and Number:
Japanese Patent JP2001520812
Kind Code:
A
Abstract:
An improved programmable logic device (PLD) comprises a programmable AND first array to which a set of PLD input lines are selectively connectable and providing a set of outputs which are selectively connectable to a set of inputs to a programmable OR second army which drives a second set of output lines, in combination with a programmable AND third array having a set of inputs that are selectively connectable to the set of input lines and having a set of outputs that are fixedly connected as a set of inputs to a fixed OR fourth array providing a set of PLD outputs, with the set of outputs from the OR second array also connected in a fixed manner as inputs to the OR fourth array. This arrangement overcomes some of the weaknesses in both the conventional PAL and PLA architectures while retaining most of their strengths.
Inventors:
Klein Ronald Lee
Application Number:
JP51155396A
Publication Date:
October 30, 2001
Filing Date:
August 30, 1995
Export Citation:
Assignee:
Philips Electronics Nemrose Fennaught Shap
International Classes:
H03K19/177; H03K19/173; (IPC1-7): H03K19/173
Attorney, Agent or Firm:
Akihide Sugimura (1 outside)