Title:
【発明の名称】パターニングされた導電層の空隙をHSQで充填した高集積度ボーダレスビア
Document Type and Number:
Japanese Patent JP2002509356
Kind Code:
A
Abstract:
Borderless vias are formed in electrical connection with a lower metal feature of a metal pattern gap filled with HSQ. Heat treatment in an inert atmosphere is conducted before filling the through-hole to outgas water absorbed during solvent cleaning of the through-hole, thereby reducing via void formation and improving via integrity.
Inventors:
Trang, Khan
Hyun, Richard Jay
Chan, Simon S
Yuh, Liu
Hyun, Richard Jay
Chan, Simon S
Yuh, Liu
Application Number:
JP2000539524A
Publication Date:
March 26, 2002
Filing Date:
December 18, 1998
Export Citation:
Assignee:
ADVANCED MICRO DEVICES INCORPORATED
International Classes:
H01L21/3105; H01L21/768; H01L23/522; (IPC1-7): H01L21/768; H01L21/312
Attorney, Agent or Firm:
Fukami Hisaro (5 others)