Title:
【発明の名称】データ依存型電圧バイアス・レベルのための回路
Document Type and Number:
Japanese Patent JP2002530921
Kind Code:
A
Abstract:
Briefly, in accordance with one embodiment, an integrated circuit includes a circuit to produce discrete output signals that include a multilevel, data dependent voltage bias level, wherein the circuit further includes the capability to at least approximately cancel a zero introduced in the frequency response of the circuit due to capacitive coupling. Briefly, in accordance with another embodiment of the invention, an integrated circuit includes at least one comparator coupled to compare input and output voltage signal levels. The integrated circuit further includes circuitry to signal for an adjustment in the output voltage signal levels based, at least in part, on the computer output signal.
Inventors:
Luke A. Johnson
Schwartz Row, John Kay
Schwartz Row, John Kay
Application Number:
JP2000583167A
Publication Date:
September 17, 2002
Filing Date:
November 05, 1999
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
H04L25/06; H03M1/12; (IPC1-7): H04L25/06
Attorney, Agent or Firm:
Masaki Yamakawa