Title:
【発明の名称】データ転送時間の調節方法、コンピュータシステム及びバス・デバイス
Document Type and Number:
Japanese Patent JP2002533832
Kind Code:
A
Abstract:
A computer system includes a bus, a first bus device, a core circuit and a second circuit. The first bus device is coupled to the bus and adapted to finish a first indication of data to a portion of a bus beginning at a first clock cycle. The bus is capable of skewing the first indication to produce a second indication of the data at another portion of the bus beginning at another clock cycle. The second circuit is coupled to the bus and is adapted to receive an indication of a selected latency time. The second circuit is also adapted to transfer the data to the core circuit in response to the second indication and regulate the transfer so that the circuit receives the data beginning at the selected latency time after the first clock cycle.
Inventors:
Holland, Kenneth
Lee, David
Meredith, Susan
Lee, David
Meredith, Susan
Application Number:
JP2000591510A
Publication Date:
October 08, 2002
Filing Date:
September 29, 1999
Export Citation:
Assignee:
Intel Corporation
International Classes:
G06F13/36; G06F11/16; G06F13/42; (IPC1-7): G06F13/42; G06F13/36
Attorney, Agent or Firm:
Okuyama Shoichi (2 outside)